MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6341/D
128K x 24 Bit Static Random
Access Memory
The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable
(G) pins, allowing for greater system flexibility and eliminating bus contention
problems.
The MCM6341 is available in a 119–bump PBGA package.
•
•
•
•
•
•
•
Single 3.3 V Power Supply
Fast Access Time: 10/11/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 280/275/270/260 mA Maximum, Active AC
Commercial Temperature (0°C to 70°C) and
Industrial Temperature (–40°C to 85°C) Options
MCM6341
ZP PACKAGE
PBGA
CASE 999–02
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2, E3 . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . No Connection
VDD . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
DQ
INPUT
DATA
CONTROL
DQ
A
E1
E2
E3
W
G
A
A
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
DQ
DQ
REV 8
10/6/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
MCM6341
1
PIN ASSIGNMENT
1
A
B
C
D
E
DQ
F
G
DQ
H
DQ
J
K
L
M
DQ
N
P
R
T
NC
U
NC
A
A
A
A
W
G
A
A
A
A
NC
NC
DQ
DQ
DQ
VDD
VSS
VDD
NC
VSS
VDD
VSS
NC
VSS
VSS
VSS
NC
VSS
VDD
VSS
NC
VDD
VSS
VDD
NC
DQ
DQ
DQ
DQ
VDD
DQ
DQ
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
DQ
VDD
DQ
DQ
VSS
VDD
VSS
VDD
VSS
DQ
DQ
VSS
VDD
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VDD
DQ
DQ
NC
NC
DQ
DQ
2
A
A
NC
VDD
3
A
A
E2
VSS
4
A
E1
NC
VSS
5
A
A
E3
VSS
6
A
A
NC
VDD
7
NC
NC
DQ
DQ
119–BUMP PBGA
TOP VIEW
MCM6341
2
MOTOROLA FAST SRAM
TRUTH TABLE
(X = Don’t Care)
E1
H
X
X
L
L
L
E2
X
L
X
H
H
H
E3
X
X
H
L
L
L
G
X
X
X
H
L
X
W
X
X
X
H
H
L
Mode
Not Selected
Not Selected
Not Selected
Output Disabled
Read
Write
I/O Pin
High–Z
High–Z
High–Z
High–Z
Dout
High–Z
Cycle
—
—
—
—
Read
Write
Current
ISB1, ISB2
ISB1, ISB2
ISB1, ISB2
IDDA
IDDA
IDDA
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VDD
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Commercial
Industrial
Symbol
VDD
Vin, Vout
Iout
PD
Tbias
Tstg
Value
–0.5 to 5.0
–0.5 to VDD + 0.5
±20
1.0
–10 to 85
–45 to 90
–55 to 150
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid ap-
plication of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Storage Temperature — Plastic
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PRODUCT CONFIGURATIONS
Power Supply
Part No.
P
N
MCM6341ZP10
MCM6341ZP11
MCM6341ZP12
MCM6341ZP15
SCM6341ZP10C
SCM6341ZP11A
SCM6341ZP12A
SCM6341ZP15A
Commercial
C
i l
±
10%
n
n
n
n
Industrial
I d
i l
+ 10%, – 5%
n
n
n
n
n
n
n
n
n
n
n
n
MOTOROLA FAST SRAM
MCM6341
3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±10%,
TA = 0° to 70°C)
(TA = –40° to 85°C for Industrial Temperature Option)
(VDD = 3.3 V +10%, –5% for 10 ns Industrial Device Only)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
Symbol
VDD
VIH
VIL
Min
3.0
2.2
–0.5
*
Typ
3.3
—
—
Max
3.6
VDD + 0.3**
0.8
Unit
V
V
V
* VIL (min) = –0.5 V dc; VIL (min) = –2.0 V ac (pulse width
≤
2.0 ns).
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width
≤
2.0 ns).
DC CHARACTERISTICS
(See Note)
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Output Low Voltage (IOL = +8.0 mA)
Output High Voltage (IOH = –4.0 mA)
Symbol
Ilkg(I)
Ilkg(O)
VOL
VOH
Min
—
—
—
2.4
Max
±1.0
±1.0
0.4
—
Unit
µA
µA
V
V
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
POWER SUPPLY CURRENTS
(See Note)
Parameter
AC Active Supply Current
(Iout = 0 mA, VDD = max)
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
Symbol
IDD
0 to 70°C
250
240
230
220
50
50
50
45
10
– 40 to
85°C
290
285
280
270
55
55
55
50
10
Unit
mA
AC Standby Current (VDD = max, E = VIH,
No other restrictions on other inputs)
ISB1
mA
CMOS Standby Current (E
≥
VDD – 0.2 V, Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V)
(VDD = max, f = 0 MHz)
ISB2
mA
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Input/Output Capacitance
All Inputs Except Clocks and DQs
E, G, W
DQ
Symbol
Cin
Cck
CI/O
Typ
4
5
5
Max
6
8
8
Unit
pF
pF
MCM6341
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±10%,
TA = 0° to 70°C)
(TA = –40° to 85°C for Industrial Temperature Option)
(VDD = 3.3 V +10%, –5% for 10 ns Industrial Device Only)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING
(See Notes 1, 2, and 3)
MCM6341–10
Parameter
P
Read Cycle Time
Address Access Time
Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
Symbol
S b l
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
Min
10
—
—
—
3
3
0
0
0
Max
—
10
10
4
—
—
—
5
5
MCM6341–11
Min
11
—
—
—
3
3
0
0
0
Max
—
11
11
4
—
—
—
6
6
MCM6341–12
Min
12
—
—
—
3
3
0
0
0
Max
—
12
12
4
—
—
—
6
6
MCM6341–15
Min
15
—
—
—
3
3
0
0
0
Max
—
15
15
4
—
—
—
7
7
Unit
U i
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
5
Notes
N
4
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device
to device.
7. Transition is measured
±200
mV from steady–state voltage.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E
≤
VIL, G
≤
VIL).
t
t
RL = 50
Ω
OUTPUT
Z0 = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM6341
5
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