Field Programmable Gate Array, 547 CLBs, 2000 Gates, 37MHz, 547-Cell, CMOS, CPGA84, CERAMIC, PGA-84
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Actel |
package instruction | CERAMIC, PGA-84 |
Reach Compliance Code | unknow |
Other features | MAX 69 I/OS |
maximum clock frequency | 37 MHz |
Combined latency of CLB-Max | 5.5 ns |
JESD-30 code | S-CPGA-P84 |
JESD-609 code | e0 |
length | 27.94 mm |
Configurable number of logic blocks | 547 |
Equivalent number of gates | 2000 |
Number of entries | 69 |
Number of logical units | 547 |
Output times | 69 |
Number of terminals | 84 |
Maximum operating temperature | 125 °C |
Minimum operating temperature | -55 °C |
organize | 547 CLBS, 2000 GATES |
Package body material | CERAMIC, METAL-SEALED COFIRED |
encapsulated code | PGA |
Encapsulate equivalent code | PGA84M,11X11 |
Package shape | SQUARE |
Package form | GRID ARRAY |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
power supply | 5 V |
Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
Certification status | Not Qualified |
Filter level | MIL-STD-883 Class S (Modified) |
Maximum seat height | 4.318 mm |
Maximum supply voltage | 5.5 V |
Minimum supply voltage | 4.5 V |
Nominal supply voltage | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | MILITARY |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | PIN/PEG |
Terminal pitch | 2.54 mm |
Terminal location | PERPENDICULAR |
Maximum time at peak reflow temperature | NOT SPECIFIED |
width | 27.94 mm |