INTEGRATED CIRCUITS
DATA SHEET
TDA8703
8-bit high-speed analog-to-digital
converter
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
1996 Aug 26
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
FEATURES
•
8-bit resolution
•
Sampling rate up to 40 MHz
•
High signal-to-noise ratio over a large analog input
frequency range (7.1 effective bits at 4.43 MHz
full-scale input)
•
Binary or two's complement 3-state TTL outputs
•
Overflow/underflow 3-state TTL output
•
TTL compatible digital inputs
•
Low-level AC clock input signal allowed
•
Internal reference voltage generator
•
Power dissipation only 290 mW (typical)
•
Low analog input capacitance, no buffer amplifier
required
•
No sample-and-hold circuit required.
ORDERING INFORMATION
TYPE
NUMBER
TDA8703
TDA8703T
PACKAGE
NAME
DIP24
SO24
DESCRIPTION
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width 7.5 mm
APPLICATIONS
TDA8703
•
General purpose high-speed analog-to-digital
conversion
•
Digital TV, IDTV
•
Subscriber TV decoder
•
Satellite TV decoders
•
Digital VCR.
GENERAL DESCRIPTION
The TDA8703 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for video and other applications.
It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL compatible, although
a low-level AC clock input signal is allowed.
VERSION
SOT101-1
SOT137-1
1996 Aug 26
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
QUICK REFERENCE DATA
SYMBOL
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ILE
DLE
AILE
B
f
CLK
/f
CLK
P
tot
Notes
1. Full-scale sinewave (f
i
= 4.4 MHz; f
CLK
; f
CLK
= 27 MHz).
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
analog supply current
digital supply current
output stages supply current
DC integral linearity error
DC differential linearity error
AC integral linearity error
−3
dB bandwidth
maximum conversion rate
total power dissipation
note 1
note 2; f
CLK
= 40 MHz
note 3
CONDITIONS
MIN.
4.5
4.5
4.2
−
−
−
−
−
−
−
40
−
TYP.
5.0
5.0
5.0
28
19
11
−
−
−
19.5
−
290
TDA8703
MAX.
5.5
5.5
5.5
36
25
14
±1
±1/2
±2
−
−
415
UNIT
V
V
V
mA
mA
mA
LSB
LSB
LSB
MHz
MHz
mW
2. The
−3
dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
1996 Aug 26
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
BLOCK DIAGRAM
TDA8703
clock inputs
handbook, full pagewidth
V CCA
7
CLK
16
CLK
17
VCCD
18
TC
21
CE
22
STABILIZER
CLOCK DRIVER
DEC 5
VRT 9
TDA8703
TDA8703T
12 D7
13 D6
14 D5
15 D4
analog
voltage input
VI 8
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
TTL OUTPUTS
23 D3
24 D2
1 D1
2 D0
VRB 4
LSB
data outputs
MSB
19
V
CCO
OVERFLOW / UNDERFLOW
LATCH
3
AGND
analog ground
20
DGND
digital ground
TTL OUTPUT
11
overflow /
underflow
output
MGA015
Fig.1 Block diagram.
1996 Aug 26
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
PINNING
SYMBOL PIN
D1
D0
AGND
V
RB
DEC
n.c.
V
CCA
VI
V
RT
n.c.
O/UF
D7
D6
D5
D4
CLK
CLK
V
CCD
V
CCO
DGND
TC
CE
D3
D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION
data output; bit 1
data output; bit 0 (LSB)
analog ground
reference voltage bottom (decoupling)
decoupling input (internal stabilization
loop decoupling)
not connected
positive supply voltage for analog
circuits (+5 V)
analog voltage input
reference voltage top (decoupling)
not connected
overflow/underflow data output
data output; bit 7 (MSB)
data output; bit 6
data output; bit 5
data output; bit 4
clock input
complementary clock input
positive supply voltage for digital
circuits (+5 V)
positive supply voltage for output
stages (+5 V)
digital ground
input for two's complement output (TTL
level input, active LOW)
chip enable input (TTL level input,
active LOW)
data output; bit 3
data output; bit 2
Fig.2 Pin configuration.
V CCA
VI
V RT
n.c.
O/UF
D7
handbook, halfpage
TDA8703
D1
D0
AGND
V RB
DEC
n.c.
1
2
3
4
5
6
7
8
9
10
11
12
MLB034
24
23
D2
D3
22 CE
21
20
19
TC
DGND
V CCO
TDA8703/
TDA8703T
18 V CCD
17
16
15
14
13
CLK
CLK
D4
D5
D6
1996 Aug 26
5
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