KMM368L6423AT
Preliminary
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.0
Sep. 1999
- -1 -
Rev. 0.0 Sep. 1999
KMM368L6423AT
Revision History
Revision 0 (Sep 1999)
1. First release for internal usage
Preliminary
184pin Unbuffered DDR SDRAM MODULE
-0-
Rev. 0.0 Sep. 1999
KMM368L6423AT
Preliminary
184pin Unbuffered DDR SDRAM MODULE
KMM368L6423AT DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
1. GENERAL DESCRIPTION
The Samsung KMM368L6423AT is 32M bit x 64 Double Data
Rate SDRAM high density memory module based on first gen.
of 256Mb DDR SDRAM respectively. The Samsung KMM368-
L6423AT consists of sixteen CMOS 32M x 8 bit with 4banks
Double Data Rate SDRAMs in 66pin TSOP-II(400mil) pack-
ages mounted on a 184pin glass-epoxy substrate. Four 0.1uF
decoupling capacitors are mounted on the printed circuit board
in parallel for each DDR SDRAM. The KMM368L6423AT Dual
In-line Memory Module and is intended for mounting into
184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2. FEATURE
• Performance range
Part No.
KMM
368L6423AT
-G(F)Z
KMM
368L6423AT
-G(F)Y
KMM
368L6423AT
-G(F)0
Max Freq.
133MHz(7.5ns@CL=2)
133MHz(7.5ns@CL=2.5)
100MHz(10ns@CL=2)
SSTL_2
Interface
• Power supply
Vdd: 2.5V
±
0.2V
Power: G - normal, F - Low power
• MRS cycle with address key programs
CAS Latency (Access from column address):2,2.5
Burst length ;2, 4, 8
Data scramble ;Sequential & Interleave
• Serial presence detect with EEPROM
• PCB :
Height 1450 (mil),
double sided component
3. PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK0
/CK0
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
A5
62
33 DQ24 63
34 VSS 64
35 DQ25 65
36 DQS3 66
37
A4
67
38 VDD 68
39 DQ26 69
40 DQ27 70
41
A2
71
42 VSS 72
43
A1
73
44 *CB0 74
45 *CB1 75
46 VDD 76
47 *DQS8 77
48
A0
78
49 *CB2 79
50 VSS 80
51 *CB3 81
52
BA1 82
KEY
83
53 DQ32 84
54 VDDQ 85
55 DQ33 86
56 DQS4 87
57 DQ34 88
58 VSS 89
59
BA0 90
60 DQ35 91
61 DQ40 92
Front
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
WP
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
CK1
/CK1
VSS
*DM8
A10
*CB6
VDDQ
*CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
/RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
V33
4. PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CKE0,CKE1
CS0, CS1
RAS
CAS
WE
DM0 ~ 7
VDD
VDDQ
VSS
VREF
V33
SDA
SCL
SA0 ~ 2
WP
VDDID
DU
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (3.3V)
Serial data I/O
Serial clock
Address in EEPROM
Write protection
VDD identification flag
Don′t use
CK0,CK0 ~ CK2, CK2 Clock input
NC
No connection
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
-1-
Rev. 0.0 Sep. 1999
KMM368L6423AT
5. Functional Block Diagram
CS1
CS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
Preliminary
184pin Unbuffered DDR SDRAM MODULE
DQS4
DM4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
D8
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D12
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS5
DM5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D1
D9
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D13
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
2
3
4
5
CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D2
D10
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D14
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS7
DM7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
D11
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
*Clock Net Wiring
Dram1
Serial PD
WP
SCL
47K
Ω
A0
SA0
A1
SA1
A2
SA2
SDA
Clock Wiring
Clock
SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/CK2
6 SDRAMs
4 SDRAMs
6 SDRAMs
Card
Edge
Dram2
R=120
Ω
Dram3
*(Cap.)
Dram4
*(Cap.)
Dram5
Dram6
*If four DRAMs are loaded,
Cap will replace DRAM3,4
BA0 - BAn
A0 - An
V
DDQ
V
DD
VREF
V
SS
V
DDID
BA0-BAn: SDRAMs D0 - D15 CKE1
A0-An: SDRAMs D0 - D15
RAS
CAS
D0 - D15
D0 - D15
D0 - D15
D0 - D15
Strap: see Note 4
CKE0
WE
CKE: SDRAMs D8 - D15
Notes:
RAS: SDRAMs D0 - D15
1. DQ-to-I/O wiring is shown as recom-
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
≠VDDQ.
CAS: SDRAMs D0 - D15
mended but may be changed.
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D15
-2-
Rev. 0.0 Sep. 1999
KMM368L6423AT
6. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Voltage on V
DDQ
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Preliminary
184pin Unbuffered DDR SDRAM MODULE
Symbol
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 4.6
-0.5 ~ 3.6
-55 ~ +150
16
50
Unit
V
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
7. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current (V
OUT
= 1.95V)
Output Low Current (V
OUT
= 0.35V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
Min
2.3
2.3
1.15
V
REF
-0.04
V
REF
+0.18
-0.3
-0.3
0.36
-5
-5
-15.2
15.2
Max
2.7
2.7
1.35
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.18
V
DDQ
+0.3
V
DDQ
+0.6
5
5
Unit
V
V
V
V
V
V
V
V
uA
uA
mA
mA
Note
1
2
3
Note
:
1. Typically, the value of V
REF
is expected to be about 0.5*V
DDQ
of the transmitting device.
V
REF
is expected to track variation in V
DDQ
.
2. Peak to peak AC noise on V
REF
may not exceed 2% V
REF
(DC).
3. V
tt
of the transmitting device must track V
REF
of the receiving device.
-3-
Rev. 0.0 Sep. 1999