Freescale Semiconductor
Advance Information
MPC8568EEC
Rev. 0, 05/2009
MPC8568E/MPC8567E
PowerQUICC III™
Integrated Processor
Hardware Specifications
Due to feature similarities, this document covers both the
MPC8568E and MPC8567E features. For simplicity,
MPC8568 may only be mentioned throughout the document.
The difference between theMPC8568E and MPC8567E is
that the MPC8567E does not have eTSEC1, eTSEC2, or
TLU. The MPC8567E PCI Express™ supports x1/x2/x4, but
does not have x8 support.
Both the MPC8568E and MPC8567E have their own pin
assignment table.
1.
2.
3.
4.
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Contents
MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ethernet Interface and MII Management . . . . . . . . . . 26
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 61
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
HDLC, BISYNC, Transparent and
Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
System Design Information . . . . . . . . . . . . . . . . . . . 130
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 136
Document Revision History . . . . . . . . . . . . . . . . . . 138
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
MPC8568E Overview
1
MPC8568E Overview
This section provides a high-level overview of MPC8568E features.
Figure 1
shows the major functional
units within the MPC8568E.
DDR
SDRAM
Flash
SDRAM
ZBT RAM
DDR/DDR2/
Memory Controller
Local Bus Controller
e500
Coherency
Module
512-Kbyte
L2 Cache/
SRAM
MPC8568
e500 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Core Complex
Bus
Table Lookup Unit
IRQs
Serial
I
2
C
I
2
C
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
Programmable Interrupt
Controller (PIC)
DUART
I
2
C Controller
I
2
C Controller
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
Parallel I/O
UCC1
UCC2
UCC3
UCC4
UCC5
UCC6
UCC7
UCC8
MCC
Security
Engine
XOR
Engine
SPI1
SPI2
Baud Rate
Generators
OceaN
Switch
Fabric
Serial RapidIO
and/or
PCI Express
32-bit PCI Bus Interface
4-Channel DMA
Controller
QUICC Engine™
Accelerators
Multi-User
RAM
Serial DMA
&
2 Virtual
DMAs
4x/1x RapidIO and/or
x4/x2/x1 PCI Express
or x8 PCI Express
PCI 32-bit
66 MHz
Dual 32-bit RISC CP
Time Slot Assigner
Serial Interface
8 TDM Ports
8 MII/
RMII
3 GMII/
2 RGMII/TBI/RTBI
2 UL2/POS
Figure 1. MPC8568E Block Diagram
1.1
Key Features
Key features of the MPC8568E include:
• High-performance Power Architecture™ e500v2 core with 36-bit physical addressing
• 512 Kbytes of level-2 cache
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
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MPC8568E Overview
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QUICC Engine
Integrated security engine with XOR acceleration
Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP
acceleration and classification capabilities
DDR/DDR2 memory controller
Table lookup unit (TLU) to access application-defined routing topology and control tables
32-bit PCI controller
A 1x/4x serial RapidIO™ and/or x1/x2/x4 PCI Express interface. If x8 PCI Express is needed, then
RapidIO is not available due to the limitation of the pin multiplexing.
Programmable interrupt controller (PIC)
Four-channel DMA controller, two I
2
C controllers, DUART, and local bus controller (LBC)
NOTE
The MPC8568E and MPC8567E are also available without a security
engine, in a configuration known as the MPC8568 and MPC8567. All
specifications other than those relating to security apply to the MPC8568
and MPC8567 exactly as described in this document.
These features are described in greater detail in subsequent sections.
1.2
MPC8568E Architecture Overview
This section contains a high-level view of the MPC8568E architecture.
1.2.1
e500 Core and Memory Unit
The MPC8568E contains a high-performance 32-bit Book E–enhanced e500v2 core that implements
Power Architecture. In addition to 36-bit physical addressing, this version of the e500 core includes:
• Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
• Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for
single-precision (32-bit) floating-point instructions.
The MPC8568E also contains 512 Kbytes of L2 cache/SRAM, as follows:
• Eight-way set-associative cache organization with 32-byte cache lines
• Flexible configuration (can be configured as part cache, part SRAM)
• External masters can force data to be allocated into the cache through programmed memory ranges
or special transaction types (stashing).
• SRAM features include the following:
— I/O devices access SRAM regions by marking transactions as snoopable (global).
— Regions can reside at any aligned location in the memory map.
— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line
accesses.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
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MPC8568E Overview
1.2.2
e500 Coherency Module (ECM) and Address Map
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of
local space and external address space. The local address map is supported by eight local access windows
that define mapping within the local 36-bit (64-Gbyte) address space.
The MPC8568E can be made part of a larger system address space through the mapping of translation
windows. This functionality is included in the address translation and mapping units (ATMUs). Both
inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of
larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO
environment.
1.2.3
•
QUICC Engine
Integrated 8-port L2 Ethernet switch
— 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port
— Each port supports four priority levels
— Priority levels used with VLAN tags or IP TOS field to implement QoS
— QoS types of traffic, such as voice, video, and data
Includes support for the following protocols:
— ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for
up to 64K ATM connections
— ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0)
— IMA and ATM Transmission convergence sub-layer
— ATM OAM handling features compatible with ITU-T I.610
— PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686 and 3153
— IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum
processing
— ATM (AAL2/AAL5) to Ethernet (IP) interworking
— Extensive support for ATM statistics and Ethernet RMON/MIB statistics.
— 256 channels of HDLC/Transparent or 128 channels of SS#7
Includes support for the following serial interfaces:
— Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or
31 Multi-PHY addresses on the POS interface each.
— Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI
— Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII
— Up to eight T1/E1/J1/E3 or DS-3 serial interfaces
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MPC8568E Overview
1.2.4
Integrated Security Engine (SEC)
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass
security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.
• Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and
3GPP
• Compatible with code written for the Freescale MPC8541E and MPC8555E devices
• XOR engine for parity checking in RAID storage applications.
• Four crypto-channels, each supporting multi-command descriptor chains
• Cryptographic execution units:
— PKEU—public key execution unit
— DEU—Data Encryption Standard execution unit
— AESU—Advanced Encryption Standard unit
— AFEU—ARC four execution unit
— MDEU—message digest execution unit
— KEU—Kasumi execution unit
— RNG—Random number generator
1.2.5
Enhanced Three-Speed Ethernet Controllers
The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs
incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps
Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs
include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.
The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache
to speed classification or other frame processing. They are IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
Some of the key features of these controllers include:
• Flexible configuration for multiple PHY interface configurations.
Table 1
lists available
configurations.
MPC8568E/MPC8567E PowerQUICC III™ Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
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