RTAX1000S-CQ352E datasheet, PDF

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RTAX1000S-CQ352E: DescriptionField Programmable Gate Array, 12096 CLBs, 1000000 Gates, 18144-Cell, CMOS, CQFP352, CERAMIC, QFP-352; CategoryProgrammable logic devices Programmable logic; File Size18MB，276 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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RTAX1000S-CQ352E Overview

Field Programmable Gate Array, 12096 CLBs, 1000000 Gates, 18144-Cell, CMOS, CQFP352, CERAMIC, QFP-352

RTAX1000S-CQ352E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
package instruction	QFF, TPAK352,2.9SQ,20
Reach Compliance Code	unknow
Other features	125000 ASIC GATES ALSO AVAILABLE
Combined latency of CLB-Max	1.11 ns
JESD-30 code	S-CQFP-F352
JESD-609 code	e0
length	48 mm
Configurable number of logic blocks	12096
Equivalent number of gates	1000000
Number of entries	516
Number of logical units	18144
Output times	516
Number of terminals	352
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	12096 CLBS, 1000000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Encapsulate equivalent code	TPAK352,2.9SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
power supply	1.5,1.5/3.3,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-STD-883 Class S (Modified)
Maximum seat height	2.89 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	48 mm

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Revision 17

RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs

Radiation Performance

• SEU-Hardened Registers Eliminate the Need for Triple-Module

Redundancy (TMR)

– Immune to Single-Event Upsets (SEU) to LET

> 37 MeV-

/mg

– SEU Rate < 10

-10

Errors/Bit-Day (worst case GEO)

• SRAM Upset Rate of <10

-10

Errors/Bit-Day with Use of Error

Detection and Correction (EDAC) IP (included) with Integrated

SRAM Scrubber

– Single-Bit Correction, Double-Bit Detection

– Variable-Rate Background Refreshing

• Total Ionizing Dose Up to 300 krad (Si, Functional)

• Single-Event Latch-Up Immunity (SEL) to LET

> 117 MeV-

/mg

• TM1019 Test Data Available

• B-Flow – MIL-STD-883B

• E-Flow – Extended Flow

• V-Flow – QML Class V per MIL-PRF-38535

Specifications

• Up to 4 Million Equivalent System Gates or 500 k Equivalent

ASIC Gates

• Up to 20,160 SEU-Hardened Flip-Flops

• Up to 840 I/Os

with

SEU-Protected Input, Output, and Enable

Registers

• Up to 540 kbits Embedded SRAM

• Manufactured on 0.15 µm CMOS Antifuse Process Technology,

7 Layers of Metal

• Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,

TM3015)

Embedded Multiply/Accumulate Blocks

(RTAX-DSP Only)

•

Processing Flows

Prototyping Options

Features

Up to 120 Multiply/Accumulate Blocks

Fully SEU- and SET-Hardened

125 MHz Performance throughout Military Temperature Range

Flexible, Cascadable Accumulate Function

RTAX-SL Low Power Option

Leading-Edge Performance

•

High-Performance Embedded FIFOs

350+ MHz System Performance

500+ MHz Internal Performance

700 Mb/s LVDS Capable I/Os

• Commercial Axcelerator Devices for Functional Verification

(RTAX™-S/SL only)

• RTAX-S/SL PROTO and RTAX-DSP PROTO Devices with

Same Functional and Timing Characteristics as Flight Unit in a

Non-Hermetic Package

• Low-Priced Reprogrammable ProASIC

3 Option for Functional

Verification (RTAX-S/SL only)

• Offers Up To 80% Saving of Static Current Compared to

Standard RTAX-S Device at Worst-Case Conditions

• Single-Chip, Nonvolatile Solution

• 1.5 V Core Voltage for Low Power

• Flexible, Multi-Standard I/Os:

– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI

– JTAG Boundary Scan Testing (as per IEEE 1149.1)

– Differential I/O Standards: LVPECL and LVDS

– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Hot-Swap with Cold-Sparing Support (Except PCI)

• Embedded Memory with Variable Aspect Ratio:

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

– ROM Emulation Capability

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug Capability

Table 1 • RTAX Family Product Profile

Device

Capacity

Equivalent System Gates

ASIC Gates

Modules

Combinatorial (C-cells)

Embedded RAM/FIFO (w/o EDAC)

Core RAM Blocks

Core RAM Bits (K = 1,024)

Embedded Multiply/Accumulate

Blocks

Clocks (segmentable)

Hardwired

Routed

I/Os

I/O Banks

User I/Os (maximum)

I/O Registers

Package

CG/LG*

Note:

RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL

250,000

30,000

1,408

2,816

54 k

–

1,000,000

125,000

6,048

12,096

162 k

–

2,000,000

250,000

10,752

21,504

288 k

–

4,000,000

500,000

20,160

40,320

120

540 k

–

2,000,000

250,000

9,856

19,712

288 k

4,000,000

500,000

18,480

36,960

120

540 k

120

198

744

624

208, 352

418

1,548

624

352

684

2,052

624, 1152

256, 352

840

2,520

1272

352

684

2,052

1272

352

840

2,520

1272

352

*The body size of the CG1272 and LG1272 packages used on the RTAX-DSP devices is slightly larger than the body size of the

CG/LG1272 used on RTAX4000S/SL devices.

February 2015

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