UPD44321181GF-A85Y datasheet, PDF

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UPD44321181GF-A85Y: DescriptionZBT SRAM, 2MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100; Categorystorage storage; File Size282KB，24 Pages; ManufacturerNEC Electronics

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UPD44321181GF-A85Y Overview

ZBT SRAM, 2MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD44321181GF-A85Y Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	37748736 bi
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44321181, 44321361

32M-BIT ZEROSB

SRAM

FLOW THROUGH OPERATION

Description

The

PD44321181 is a 2,097,152-word by 18-bit and the

PD44321361 is a 1,048,576-word by 36-bit ZEROSB

static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44321181 and

PD44321361 are optimized to eliminate dead cycles for read to write, or write to read

transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and

output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input

(CLK).

The

PD44321181 and

PD44321361 are suitable for applications which require synchronous operation, high

speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

PD44321181 and

PD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness

for high density and low capacitive loading.

Features

•

Low voltage core supply: V

= 3.3 ± 0.165 V / 2.5 ± 0.125 V

•

Synchronous operation

•

Operating temperature : T

= 0 to 70 °C (-A75, -A85)

= –40 to +85 °C (-A75Y, -A85Y)

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for flow through operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 7.5 ns (117 MHz), 8.5 ns (100 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4 (

PD44321361)

/BW1 and /BW2 (

PD44321181)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

Document No. M15958EJ4V0DS00 (4th edition)

Date Published November 2003 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2002

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