SPT574
FAST, COMPLETE 12-BIT
µ
P COMPATIBLE
A/D CONVERTER WITH SAMPLE/HOLD
FEATURES
• Improved Version of the HADC574Z
• Complete 12-Bit A/D Converter with Sample/Hold,
Reference and Clock
• Low Power Dissipation (100 mW Max)
• 12-Bit Linearity (Over Temp)
• 25
µs
Max Conversion Time
• Single +5 V Supply
• Full Bipolar and Unipolar Input Range
APPLICATIONS
•
•
•
•
•
Data Acquisition Systems
8 or 12-Bit
µP
Input Functions
Process Control Systems
Test and Scientific Instruments
Personal Computer Interface
GENERAL DESCRIPTION
The SPT574 is a complete, 12-bit successive approximation
A/D converter manufactured in CMOS technology. The de-
vice is an improved version of the HADC574Z. Included on
chip are an internal reference, clock, and a sample-and-hold.
The S/H is an additional feature not available on similar
devices.
The SPT574 features 25
µs
(max) conversion time of 10 or
20 V input signals. Also, a three-state output buffer is added
for direct interface to an 8, 12, or 16-bit
µP
bus.
The SPT574 has standard bipolar and unipolar input ranges
of 10 V and 20 V that are controlled by a bipolar offset pin and
laser trimmed for specified linearity, gain and offset accuracy.
The power supply is +5 V. The device also has an optional
mode control voltage which may be used depending on the
application. With a maximum dissipation of 100 mW at the
specified voltages, power consumption is about five times
lower than that of currently available devices.
The SPT574 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages in the commercial temperature
range.
BLOCK DIAGRAM
Nibble A
Output
Nibble B
Three-State Buffers And Control
Nibble C
STS
12-Bit SAR
+
Comp
Clock
12-Bit
Capacitance
DAC
-
Offset/Gain
Trim
Control Logic
Ref
20 V In
10 V In
BIP Off
12/8
CS
Ao
R/C
CE
Ref Out
AGND
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
Mode Control Voltage (V
EE
to DGND) .................... 0 to +7 V
Logic Supply Voltage (V
DD
to DGND) ...................0 to +7 V
Analog to Digital Ground (AGND to DGND) .................
±1
V
Input Voltages
Control Input Voltages (to DGND)
(CE, CS, Ao, 12/8, R/C) ......................... -0.5 to V
DD
+0.5 V
Analog Input Voltage (to AGND)
(REF IN, BIP OFF, 10 V
IN
) ......................................
±16.5
V
20 V V
IN
Input Voltage (to AGND) ..............................
±24
V
Note:
Output
Reference Output Voltage .............. Indefinite Short to GND
Momentary Short to V
DD
Temperature
Operating Temperature, Ambient .................... 0 to +70
°C
Junction ......................... +165
°C
Lead Temperature, (Soldering 10 Seconds) ........... +300
°C
Storage Temperature .................................... -65 to +150
°C
Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
= 0 to +5 V, V
DD
= +5 V, f
S
= 40 kHz, f
IN
= 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Resolution
Linearity Error
Differential Linearity
Unipolar Offset; 10 V, 20 V
Bipolar Offset;
±5
V,
±10
V
Full Scale Calibration Error
1
Full Scale Calibration Error
1
Temperature Coefficients
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Power Supply Rejection
+4.75 V<V
DD
<+5.25 V
Analog Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
T
A
= 0 to +70
°C
No Missing Codes
+25
°C
Adjustable to Zero
+25
°C
Adjustable to Zero
+25
°C
Adjustable to Zero
VI
VI
VI
VI
VI
VI
V
V
V
V
Max Change in Full
Scale Calibration
VI
0.47
±1.0
±2.0
±12
12
12
±1
12
±2
±10
0.3
0.37
±1.0
±2.0
±12
±0.5
12
±0.5
±2
±4
0.3
Bits
LSB
Bits
LSB
LSB
% of FS
% of FS
ppm/°C
ppm/°C
ppm/°C
No Adjustment to Zero
T
A
= 0 to +70
°C
Using Internal Reference
±0.5
LSB
VI
VI
VI
VI
VI
VI
-5
-10
0
0
15
60
21
84
+5
+10
+10
+20
-5
-10
0
0
15
60
21
84
+5
+10
+10
+20
Volts
Volts
Volts
Volts
kΩ
kΩ
SPT574
2
8/1/00
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
= 0 to +5 V, V
DD
= +5 V, f
S
= 40 kHz, f
IN
= 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Power Supplies Operating
Voltage Range
V
DD
V
EE2
Operating Current
I
DD
I
EE
2
Power Dissipation
Internal Reference
Voltage
Output Current
3
DIGITAL CHARACTERISTICS
Logic Inputs
(CE, CS , R/C , Ao, 12/8 )
Logic 0
Logic1
Current
Capacitance
Logic Outputs
(DB11-DB0, STS)
Logic 0
Logic 1
Leakage
Capacitance
AC Accuracy
Spurious Free Dyn. Range
Total Harmonic Distortion
Signal-to-Noise Ratio
Signal-to-Noise & Distortion
(SINAD)
Intermodulation Distortion
f
S
=40 kHz, f
IN
=10 kHz
V
V
V
V
78
-77
72
71
78
-77
72
71
dB
dB
dB
dB
VI
VI
VI
V
-0.5
2.0
-5.0
0. 1
5
+0.8
5.5
5.0
-0.5
2.0
-5.0
0. 1
5
+0.8
5.5
5.0
Volts
Volts
µA
pF
IV
IV
IV
IV
VI
VI
VI
+4.5
+5.5
V
DD
13
167
65
20
100
2.6
+4.5
+5.5
V
DD
13
167
65
20
100
2.6
Volts
Volts
mA
µA
mW
Volts
mA
V
EE
= +5 V
2.4
0.5
2.5
2.4
0.5
2.5
(I
Sink
= 1.6 mA)
(I
SOURCE
= 500
µA)
(High Z State,
DB11-DB0 Only)
VI
VI
VI
V
+0.4
+2.4
-5
0.1
5
+5
+2.4
-5
0.1
5
+0.4
+5
Volts
Volts
µA
pF
V
-75
-75
dB
f
IN
=10 kHz;
f
IN2
=11.5 kHz
Note 1: Fixed 50
Ω
resistor from REF OUT to REF IN and REF OUT to BIP OFF.
Note 2: V
EE
is optional and is only used to set the mode for the internal sample/hold. When not using V
EE
, the pin should be treated
as a no connect. If V
EE
is connected to 0 to -15 V, aperture delay (t
AP
) will increase from 20 ns (typ) to 4000 ns (typ).
Note 3: Available for external loads; external load should not change during conversion.
SPT574
3
8/1/00
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
= 0 to +5 V, V
DD
= +5 V, f
S
= 40 kHz, f
IN
= 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
SPT574C
MIN
TYP
MAX
SPT574B
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
4
Convert Mode Timing
t
DSC
STS Delay from CE
t
HEC
CE Pulse Width
t
SSC
CS to CE Setup
t
HSC
CS Low during CE High
t
SRC
R/C to CE Setup
t
HRC
R/C Low During CE High
t
SAC
Ao to CE Setup
t
HAC
Ao Valid During CE High
t
C
Conversion Time
5
12-Bit Cycle
8-Bit Cycle
Read Mode Timing
t
DD
Access Time from CE
t
HD
Data Valid After CE Low
t
HL
Output Float Delay
t
SSR
CS to CE Setup
t
SRR
R/C to CE Setup
t
SAR
Ao to CE Setup
t
HSR
CS Valid After CE Low
t
HRR
R/C High After CE Low
t
HS
STS Delay After Data Valid
t
HAR
Ao Valid after CE Low
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
60
30
20
20
0
20
20
22
16
75
35
100
0
25
25
18
150
25
150
50
0
50
0
1000
0
300
50
200
50
50
50
50
50
0
50
60
30
20
20
0
20
20
22
16
75
35
100
0
25
25
18
150
150
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
1000
ns
ns
ns
50
50
50
50
50
0
50
25
50
0
50
0
0
300
50
400
400
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
CE
CE
CS
t
SSC
t
HEC
CS
t
SSR
t
HSR
t
HRR
t
SRC
R/C
t
HSC
R/C
t
SRR
t
HRC
Ao
Ao
t
SAC
STS
t
SAR
t
HAR
t
HAC
STS
t
DSC
t
C
t
HS
HIGH
DB11-DB0
IMPEDANCE
DATA
VALID
t
HD
DB11-DB0
High Impedance
t
DD
t
HL
SPT574
4
8/1/00
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
= 0 to +5 V, V
DD
= +5 V, f
S
= 40 kHz, f
IN
= 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
SPT574C
MIN
TYP
MAX
SPT574B
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
4
Stand-Alone Mode Timing
t
HRL
Low R/C Pulse Width
t
DS
STS Delay from R/C
t
HDR
Data Valid After R/C Low
t
HS
STS Delay After Data Valid
t
HRH
High R/C Pulse Width
t
DDR
Data Access Time
Sample-and-Hold
Aperture Delay
Aperture Uncertainty Time
VI
VI
VI
VI
VI
VI
V
EE
= +5 V
V
EE
= +5 V
IV
V
25
300
100
400
25
200
1000
150
20
300
20
300
25
300
100
400
25
200
1000
150
ns
ns
ns
ns
ns
ns
ns
ps, RMS
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
Figure 3 - Low Pulse for R/C - Outputs Enabled
After Conversion
t
R/C
HRL
Figure 4 - High Pulse for R/C - Outputs Enabled While
R/C is High, Otherwise High Impedance
R/C
t
HRH
t
DS
t
DS
STS
t
t
t
C
STS
t
t
HDR
C
t HS
DB11-DB0
HIGH-Z
DDR
HDR
HIGH-Z
DATA VALID
DB11-DB0
DATA VALID
DATA VALID
SPT574
5
8/1/00
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