KSZ8895MQX/RQX/FQX/MLX
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Features
Advanced Switch Features
• IEEE 802.1q VLAN Support for up to 128 Active
VLAN Groups (Full-Range 4096 of VLAN IDs)
• Static MAC Table Supports up to 32 Entries
• VLAN ID Tag/Untagged Options, Per Port Basis
• IEEE 802.1p/q Tag Insertion or Removal on a Per
Port Basis Based on Ingress Port (Egress)
• Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
• Jitter-Free Per Packet Based Rate Limiting Sup-
port
• Broadcast Storm Protection with Percentage Con-
trol (Global and Per Port Basis)
• IEEE 802.1d Rapid Spanning Tree Protocol RSTP
Support
• Tail Tag Mode (1 Byte Added Before FCS) Sup-
port at Port 5 to Inform the Processor Which
Ingress Port Receives the Packet
• 1.4 Gbps High-Performance Memory Bandwidth
and Shared Memory Based Switch Fabric with
Fully Non-Blocking Configuration
• Dual MII with MAC 5 and PHY 5 on Port 5, SW5-
MII/RMII for MAC 5 and P5-MII/RMII for PHY 5
• Enable/Disable Option for Huge Frame Size up to
2000 Bytes Per Frame
• IGMP v1/v2 Snooping (IPv4) Support for Multicast
Packet Filtering
• IPv4/IPv6 QoS Support
• Support Unknown Unicast/Multicast Address and
Unknown VID Packet Filtering
• Self-Address Filtering
Comprehensive Configuration Register Access
• Serial Management Interface (MDC/MDIO) to All
PHYs Registers and SMI Interface (MDC/MDIO)
to All Registers
• High-Speed SPI (up to 25 MHz) and I
2
C Master
Interface to all Internal Registers
• I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch Mode
• Control Registers Configurable on the Fly (Port-
Priority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
• Per Port, 802.1p and DiffServ-Based
• 1/2/4-Queue QoS Prioritization Selection
2016 Microchip Technology Inc.
• Programmable Weighted Fair Queuing for Ratio
Control
• Re-Mapping of 802.1p Priority Field Per Port
Basis
Integrated 5-Port 10/100 Ethernet Switch
• New Generation Switch with Five MACs and Five
PHYs that are Fully Compliant with the IEEE
802.3u Standard
• PHYs Designed with Patented Enhanced Mixed-
Signal Technology
• Non-Blocking Switch Fabric Ensures Fast Packet
Delivery by Utilizing a 1K MAC Address Lookup
Table and a Store-and-Forward Architecture
• On-Chip 64Kbyte Memory for Frame Buffering
(Not Shared with 1K Unicast Address Table)
• Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
• Half-Duplex Back Pressure Flow Control
• HP Auto MDI/MDI-X and IEEE Auto Crossover
Support
• SW-MII Interface Supports Both MAC Mode and
PHY Mode
• 7-Wire Serial Network Interface (SNI) Support for
Legacy MAC
• Per Port LED Indicators for Link, Activity, and 10/
100 Speed
• Register Port Status Support for Link, Activity,
Full-/Half-Duplex and 10/100 Speed
• LinkMD
®
Cable Diagnostic Capabilities
• On-Chip Terminations and Internal Biasing Tech-
nology for Cost Down and Lowest Power Con-
sumption
Switch Monitoring Features
• Port Mirroring/Monitoring/Sniffing: Ingress and/or
Egress Traffic to Any Port or MII
• MIB Counters for Fully Compliant Statistics Gath-
ering; 34 MIB Counters Per Port
• Loopback Support for MAC, PHY, and Remote
Diagnostic of Failure
• Interrupt for the Link Change on Any Ports
Low-Power Dissipation
• Full-Chip Hardware Power-Down
• Full-Chip Software Power-Down and Per Port
Software Power-Down
• Energy-Detect Mode Support <100 mW Full-Chip
Power Consumption When All Ports Have No
DS00002246A-page 1
KSZ8895MQX/RQX/FQX/MLX
•
Activity
Very-Low Full-Chip Power Consumption (<0.5W)
in Standalone 5-Port, without Extra Power Con-
sumption on Transformers
Dynamic Clock Tree Shutdown Feature
Voltages: Single 3.3V Supply with 3.3V V
DDIO
and
Internal 1.2V LDO Controller Enabled, or External
1.2V LDO Solution
- Analog V
DDAT
3.3V Only
- V
DDIO
Support 3.3V, 2.5V, and 1.8V
- Low 1.2V Core Power
Commercial Temperature Range: 0°C to +70°C
Industrial Temperature Range: –40°C to +85°C
Available in 128-pin PQFP and 128-pin LQFP,
Lead-Free Packages
•
•
•
•
•
Target Applications
•
•
•
•
•
•
•
•
•
•
Typical
VoIP Phone
Set-Top/Game Box
Industrial Control
IPTV POF
SOHO Residential Gateway
Broadband Gateway/Firewall/VPN
Integrated DSL/Cable Modem
Wireless LAN Access Point + Gateway
Standalone 10/100 5-Port Switch
DS00002246A-page 2
2016 Microchip Technology Inc.
KSZ8895MQX/RQX/FQX/MLX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site;
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
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Register on our web site at
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to receive the most current information on all of our products.
2016 Microchip Technology Inc.
DS00002246A-page 3
KSZ8895MQX/RQX/FQX/MLX
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 5
2.0 Pin Description and Configuration ................................................................................................................................................... 6
3.0 Functional Description ................................................................................................................................................................... 20
4.0 Register Descriptions .................................................................................................................................................................... 46
5.0 Operational Characteristics ........................................................................................................................................................... 87
6.0 Electrical Characteristics ............................................................................................................................................................... 88
7.0 Timing Diagrams ............................................................................................................................................................................ 90
8.0 Reset Circuit................................................................................................................................................................................. 100
9.0 Selection of Isolation Transformer ............................................................................................................................................... 101
10.0 Package Outline......................................................................................................................................................................... 102
Appendix A: Data Sheet Revision History ......................................................................................................................................... 104
The Microchip Web Site .................................................................................................................................................................... 105
Customer Change Notification Service ............................................................................................................................................. 105
Customer Support ............................................................................................................................................................................. 105
Product Identification System ............................................................................................................................................................ 106
DS00002246A-page 4
2016 Microchip Technology Inc.
KSZ8895MQX/RQX/FQX/MLX
1.0
1.1
INTRODUCTION
General Description
The KSZ8895MQX/RQX/FQX/MLX is a highly-integrated, Layer 2 managed, five-port switch with numerous features
designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power con-
sumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and
shared memory-based switch fabric with non-blocking configuration. Its extensive feature set includes power manage-
ment, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four-queue QoS prioritization,
management interfaces, and MIB counters. The KSZ8895 family provides multiple CPU data interfaces to effectively
address both current and emerging fast Ethernet applications when Port 5 is configured to separate MAC5 with SW5-
MII/RMII and PHY5 with P5-MII/RMII interfaces.
The KSZ8895 family offers three configurations, providing the flexibility to meet different requirements:
• KSZ8895MQX/MLX: Five 10/100Base-T/TX transceivers, One SW5-MII, and One P5-MII interface
• KSZ8895RQX: Five 10/100Base-T/TX transceivers, One SW5-RMII, and One P5-RMII interface
• KSZ8895FQX: Four 10/100Base-T/TX transceivers on Ports 1, 2, 3, and 5 (port 3 can be set to fiber mode). One
100Base-FX transceiver on Port 4. One SW5-MII and One P5-MII interface
All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed
through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode.
KSZ8895MQX/RQX/FQX are available in the 128-pin PQFP package. KSZ8895MLX is available as a 128-pin LQFP
package.
FIGURE 1-1:
FUNCTIONAL DIAGRAM
KSZ8895MQX/RQX/FQX/MLX
AUTOMDI/MDIX
10/100
T/TX
PHY1
10/100
T/TX
PHY2
10/100
T/TX/FX
PHY3
10/100
T/TX/FX
PHY4
10/100
T/TX
PHY5
10/100
MAC1
10/100
MAC2
10/100
MAC3
10/100
MAC4
10/100
MAC5
LOOK UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
FIFO, FLOW CONTROL, VLAN TAGGING, PROIRITY
AUTOMDI/MDIX
AUTOMDI/MDIX
AUTOMDI/MDIX
AUTOMDI/MDIX
P5-MII/RMII
MDC/MDIO FOR MIIM AND SMI
SW5-MII/RMII OR SNI
CONTROL REG SPI I/F
LED
LED
LED
SPI
LED I/F
CONTROL
REGISTERS
2016 Microchip Technology Inc.
DS00002246A-page 5
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