SRAM
Austin Semiconductor, Inc.
512K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-95600
• SMD 5962-95613
• MIL STD-883
AS5C4008
PIN ASSIGNMENT
(Top View)
32-Pin DIP (CW), 32-Pin LCC (EC)
32-Pin SOJ (ECJ)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O7
I/O6
I/O5
I/O4
I/O3
FEATURES
•
•
•
•
•
•
High Speed: 12, 15, 17, 20, 25, 35 and 45ns
High-performance, low power military grade device
Single +5V ±10% power supply
Easy memory expansion with CE\ and OE\ options
All inputs and outputs are TTL-compatible
Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
OPTIONS
•
Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
•
Operating Temperature Range
Military: -55
o
C to +125
o
C
Industrial: -40
o
C to +85
o
C
•
Packages
Ceramic Dip (600 mil)
Ceramic Flatpack
Ceramic LCC
Ceramic SOJ
Ceramic LCC (contact factory)
• Options
2V data retention/ low power
MARKING
-12
-15
-17
-20
-25
-35
-45
XT
IT
CW
F
EC
ECJ
ECA
L
No. 112
No. 304
No. 209
No. 502
No. 208
32-Pin Flat Pack (F)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O7
I/O6
I/O5
I/O4
I/O3
GENERAL DESCRIPTION
The AS5C4008 is a 4 megabit monolithic CMOS SRAM,
organized as a 512K x 8.
The evolutionary 32 pin device allows for easy upgrades from
the 1 meg SRAM.
For flexibility in high-speed memory applications, ASI offers
chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibil-
ity in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all
inputs are fully TTL-Compatible.
AS5C4008
Rev. 6.2 06/05
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2
32 31 30
5
29
1
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
A12
A14
A16
A18
Vcc
A15
A17
NOTE:
Not all combinations of operating temperature, speed, data retention and
low power are necessarily available. Please contact factory for availability of specific part
number combinations.
32-Pin LCC (ECA)
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
AS5C4008
FUNCTIONAL BLOCK DIAGRAM
Vcc
GND
Row Decoder
Input Buffer
A0:A18
2,097,152 Bit
Memory Array
I/O Control
I/O7
I/O1
CE\
OE\
WE\
Column Decoder
Power
Down
TRUTH TABLE
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
DQ
POWER
High-Z STANDBY
Q
ACTIVE
High-Z ACTIVE
D
ACTIVE
AS5C4008
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss...................-.5V to +7.0V
Storage Temperature ............................................-65°C to +150°C
Short Circuit Output Current (per I/O)….............................20mA
Voltage on any Pin Relative to Vss......................-.5V to Vcc+1 V
Maximum Junction Temperature**....................................+150°C
AS5C4008
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above
those indicated in the operation section of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
** Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C<T
A
<125
o
C or -40
o
C to +85
o
C; Vcc = 5V +10%)
PARAMETER
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITION
SYMBOL
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
Vcc
MIN
2.2
-0.5
-10
-10
2.4
---
4.5
MAX
-20
225
180
60
30
25
10
OV < V
IN
< Vcc
Output(s) disabled
OV < V
OUT
< Vcc
I
OH
= -4.0 mA
I
OL
= 8.0 mA
MAX
V
CC
+0.5
0.8
10
10
--
0.4
5.5
UNITS
V
V
µΑ
µΑ
V
V
V
NOTES
1
1, 2
1
1
1
PARAMETER
Power Supply Current:
Operating
CONDITIONS
CE\ < V
IL
; Vcc = MAX
f = MAX = 1/t
RC
Outputs Open
L Version Only
CE\ > V
IH
; Vcc = MAX
f = 0, Outputs Open
SYM
I
CCSP
I
CCLP
I
SBTSP
I
SBTLP
I
SBCSP
I
SBCLP
-12
225
180
60
30
25
10
-15
225
180
60
30
25
10
-17
225
180
60
30
25
10
-25
225
180
60
30
25
10
-35
225
180
60
30
25
10
-45
225
180
60
30
25
10
UNITS NOTES
mA
mA
mA
mA
mA
mA
3
Power Supply Current:
Standby
L Version Only
CE\ < V
CC
-0.2V; Vcc = MAX
V
IN
< Vss +0.2V or
V
IN
> Vcc -0.2V; f = 0
L Version Only
CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
CONDITIONS
T
A
= 25 C, f = 1MHz
V
IN
= 0
o
SYMBOL
C
I
Co
MAX
12
14
UNITS
pF
pF
NOTES
4
4
AS5C4008
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS5C4008
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C<T
A
<125
o
C or -40
o
C to +85
o
C; Vcc = 5V +10%)
DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold From Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Acess Time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
WRITE CYCLE
WRITE Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Address Hold From End of Write
WRITE Pulse Width
Data Setup Time
Data Hold Time
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
0
0
12
12
12
0
1
12
6.5
0
0
0
6.5
6.5
2
2
0
6.5
7
0
0
15
15
15
0
0
15
7
0
0
0
7
7
-12
MIN
12
12
12
2
2
0
7
8
0
0
17
16
16
0
1
16
9
0
0
0
8
8
MAX
MIN
15
15
15
2
2
0
8
8
0
0
20
17
17
0
1
17
10
0
0
0
8
8
-15
MAX
-17
-20
-25
-35
-45
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
17
17
17
2
2
0
8
10
0
0
25
20
20
0
1
20
12
0
0
0
10
10
20
20
20
2
2
0
10
12
0
0
35
30
30
0
1
30
20
0
0
0
25
15
25
25
25
2
2
0
15
15
0
0
45
35
35
0
1
35
25
0
0
0
30
20
35
35
35
2
2
0
20
25
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
AS5C4008
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................................... Vss to 3.0V
Input rise and fall times ....................................................... 3ns
Input timing reference levels ............................................ 1.5V
Output reference levels ..................................................... 1.5V
Output load ............................................... See Figures 1 and 2
AS5C4008
Q
167 ohms
1.73V
C=30pF
Q
167 ohms
1.73V
C=5pF
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1.
2.
3.
4.
5.
6.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
7.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of any
product in which the junction temperature exceeds
150°C. Care should be taken to limit power to acceptable
levels.
8.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
(L Version Only)
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
CE\ > (Vcc -0.2V)
VIN > (Vcc -0.2V) or < 0.2V
V
CC
= 2V
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
0
10
MIN
2
4.5
MAX
UNITS
V
mA
ns
ms
4
4, 11
NOTES
AS5C4008
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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