PIC18F46J11
PIC18F46J11 Family
Silicon Errata and Data Sheet Clarification
The PIC18F46J11 family devices that you have received
conform functionally to the current Device Data Sheet
(DS39932D), except for the anomalies described in this
document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F46J11 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of
Table 2
apply
to the current silicon revision (A4).
5.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window >
Dashboard
and click the
Refresh Debug
Tool Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
Data Sheet clarifications and corrections start on
page 9,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC18F46J11
family silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Part Number
Device
ID
(1)
Revision ID for Silicon Revision
(2)
A2
A4
PIC18F24J11
PIC18F25J11
PIC18F26J11
PIC18F44J11
PIC18F45J11
PIC18F46J11
PIC18LF24J11
PIC18LF25J11
PIC18LF26J11
PIC18LF44J11
PIC18LF45J11
PIC18LF46J11
Note 1:
2:
0x26Ch
0x26Dh
0x26Eh
0x26Fh
0x270h
0x271h
0x272h
0x273h
0x274h
0x275h
0x276h
0x277h
2h
4h
The Device IDs (DEVID and REVID) are located at the last two implemented addresses of configuration memory space.
They are shown in hexadecimal in the format, “DEVID:REVID”.
Refer to the
“PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification”
(DS39687) for detailed
information on Device and Revision IDs for your specific device.
2009-2013 Microchip Technology Inc.
DS80000435K-page 1
PIC18F46J11
TABLE 2:
Module
MSSP
SILICON ISSUE SUMMARY
Feature
I
2
C™
Mode
I
2
C™ Slave
Reception
Enable/
Disable
F
OSC
/2 Clock
PSP/PMP
Deep Sleep
Item
Number
1.
Issue Summary
If a Stop condition occurs in the middle of an address
or data reception, there will be issues with the SCL
clock stream and RCEN bit.
In I
2
C™ slave reception, the module may have
problems receiving correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
CY
delay.
F
OSC
/2 A/D Conversion mode may not meet linearity
error limits.
The data bus may not work correctly.
Wake-up events that occur during Deep Sleep entry
may not generate an event.
Minimum operating voltage (V
DD
)
Parameter F devices is 2.25V.
T1DIG Configuration bit is not implemented.
When MSSP1 is in I
2
C™ mode, the RB4 and RB5
pins may have extraneous pulses.
At high V
DD
voltages, performing an A/D conversion
on Channel 15 could have issues.
V
DD
voltages below the LVDSTAT threshold can
cause the constant current source to turn off.
ANx pin may output pull-up pulse during acquisition.
Spurious timer interrupt flag generation is possible
when writing to the timer in Async Timer mode.
Affected
Revisions
(1)
A2
X
A4
X
MSSP
EUSART
A/D
PMP
Low Power
Modes
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DC Characteristics
Supply
Voltage
Special Features
T1DIG
MSSP
A/D
CTMU
A/D Converter
Timer1/Timer3
Note 1:
Port 1
Band Gap
Reference
Constant
Current
Sample
Acquisition
Async Timer
Interrupts
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80000435K-page 2
2009-2013 Microchip Technology Inc.
PIC18F46J11
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
2. Module: Master Synchronous Serial Port
(MSSP)
When configured for I
2
C slave reception, the
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial
Receive/Transmit
Buffer
Register
(SSPBUF) is not read after the SSPIF interrupt
(PIR1<3>) has occurred, but before the first rising
clock edge of the next byte being received.
Work around
The issue can be resolved in either of these
ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature. This is done by
setting the SEN bit (SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
A2
X
A4
X
1. Module: Master Synchronous Serial Port
In Master I
2
C™ Receive mode, if a Stop
condition occurs in the middle of an address or
data reception, the SCL clock stream will
continue endlessly and the RCEN bit of the
SSPCON2 register will remain improperly set.
When a Start condition occurs after the improper
Stop condition, nine additional clocks will be
generated, followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop
condition, and subsequently, the stuck RCEN
bit. Clear the stuck RCEN bit by clearing the
SSPEN bit of SSPCON1.
Affected Silicon Revisions
A2
X
A4
X
2009-2013 Microchip Technology Inc.
DS80000435K-page 3
PIC18F46J11
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
(RCSTAx<7>) =
0)
• The EUSART is re-enabled
(RCSTAx<7> =
1)
• A two-cycle instruction is executed immediately
after setting SPEN, CREN or TXEN =
1
Work around
Add a 2 T
CY
delay after any instruction that
re-enables the EUSART module (sets SPEN,
CREN or TXEN =
1).
See
Example 1.
Affected Silicon Revisions
A2
X
A4
X
EXAMPLE 1:
RE-ENABLING AN EUSART MODULE
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
RCSTA1, SPEN
;or RCSTA2 if EUSART2
nop
;1 Tcy delay
nop
;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
4. Module: 10-Bit Analog-to-Digital
Converter (A/D)
When the A/D conversion clock select bits are
set for F
OSC
/2 (ADCON1<2:0> =
000),
the
Integral Linearity Error (E
IL
), parameter (A03)
and Differential Linearity Error (E
DL
), parameter
(A04), may exceed data sheet specifications.
Work around
Select one of the alternate A/D clock sources
shown in
Table 3.
5. Module: Parallel Master Port (PMP)
When configured for Parallel Slave Port
(PMMODEH<1:0> =
00
and PMPEN =
1),
the
data bus (PMD<7:0>) may not work correctly.
Incorrect data could be captured in the
PMDIN1L register.
When configured for Parallel
Master
Port
(PMMODEH<1:0> =
1x
and PMPEN =
1),
clearing a PMEx bit to disable a PMP address
line also disables the corresponding PMDx data
bus line.
Work around
None.
Affected Silicon Revisions
TABLE 3:
ALTERNATE ADC SETTINGS
Clock Setting
F
OSC
/64
F
OSC
/16
F
OSC
/4
F
RC
F
OSC
/32
F
OSC
/8
ADCON1<2:0>
ADCS<2:0>
110
101
100
011
010
001
A2
X
A4
Affected Silicon Revisions
A2
X
A4
X
DS80000435K-page 4
2009-2013 Microchip Technology Inc.
PIC18F46J11
6. Module: Low-Power Modes (Deep Sleep)
Entering Deep Sleep mode takes approximately
2 T
CY
, following the
SLEEP
instruction. Wake-up
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value Registers Read Synchronization
bit (RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the
SLEEP
instruction, but before the Deep Sleep mode has
been fully entered.
The A4 revision silicon allows insertion of a
single instruction between setting the Deep
Sleep Enable bit (DSEN, DSCONH<7>) and
issuing the
SLEEP
instruction (see
Example 2).
The insertion of a
NOP
instruction before the
SLEEP
instruction eliminates the 2 T
CY
window
where wake-up events could be missed.
Before using this work around, users should
check their device’s revision ID bits to verify that
they have the A4 silicon. This can be done at run
time by a table read from address, 3FFFFEh.
On A2 revision silicon devices, the instruction
cannot be inserted between setting the DSEN
bit and executing the
SLEEP
instruction, or the
device will enter conventional Sleep mode, not
Deep Sleep.
On A4 silicon devices, if the firmware
immediately executes
SLEEP
after setting
DSEN, the device will enter Deep Sleep mode
without benefiting from this work around.
EXAMPLE 2:
DEEP-SLEEP WAKE-UP WORK AROUND
;
;
;
;
;
;
Enter Deep Sleep mode on SLEEP instruction
Not compatible with A2 silicon
Enter Deep Sleep mode
Add code here to handle wake up events that may
have been asserted prior to Deep Sleep entry
re-attempt Deep Sleep entry if desired
EnterDeepSleep:
bsf
DSCONH, DSEN
nop
sleep
(…)
goto
EnterDeepSleep
Affected Silicon Revisions
A2
X
A4
X
2009-2013 Microchip Technology Inc.
DS80000435K-page 5
PCB Design
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