Spansion
®
Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS705-00012-1v0-E
32-bit Microcontroller
FR Family FR81S
MB91580L Series
MB91F585LA/F585LB/F585LC/F585LD/
MB91F586LA/F586LB/F586LC/F586LD/
MB91F587LA/F587LB/F587LC/F587LD
DESCRIPTION
This series has Fujitsu 32-bit microcontrollers for automobile motor control. They use the FR81S CPU that
is compatible with the FR family.
Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor
Limited.
FEATURES
FR81S CPU Core
32-bit RISC, load/store architecture, pipeline 5-stage structure
Maximum operating frequency: 128MHz (Source oscillation= 4.0MHz, 32 multiplied ( PLL clock
multiplication system) )
General-purpose register: 32 bits, 16 sets
16-bit fixed length instructions (basic instructions), 1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instructions
Bit manipulation instructions
Barrel shift instructions
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead decrement during branch process
Register interlock function
Easy assembler writing
Built-in multiplier and instruction level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.12
MB91580L Series
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for instructions and data.
Control access privilege in both privilege mode and user mode
Built-in FPU (floating-point operation)
IEEE754 compliant
Floating-point register: 32 bits
16 sets
Clock generation (SSCG function is available)
Main oscillation (4 to 20 MHz)
PLL multiplication rate:1 to 32 times
CR oscillation
Oscillation frequency: 100kHz, with frequency precision
10%
Trimming is enabled
To be used as a count clock of hardware watchdog
MB91F585LC/F586LC/F587LC/F585LD/F586LD/F587LD: Oscillation stop feature during stand-by
is not available
MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB: Oscillation stop feature during stand-by
is available
Built-in program flash memory capacity
MB91F585L: 512+64 Kbytes
MB91F586L: 768+64 Kbytes
MB91F587L: 1024+64 Kbytes
Built-in data flash (WorkFlash) 64 Kbytes
Built-in RAM capacity
Main RAM
MB91F585L: 48 Kbytes
MB91F586L: 64 Kbytes
MB91F587L: 96 Kbytes
Backup RAM 8 Kbytes
General-purpose ports:
MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC 98 ports
MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD 111 ports
Including eight I
2
C pseudo open drain corresponding ports
External bus interface (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD)
Maximum operating frequency: 40MHz
22-bit address, 16-bit data
DMA controller
Up to 8 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and software)
External interrupt input: 8 channels
Level ("H" / "L") or edge detection (rising or falling) enabled
Multi-function serial communication (built-in transmission/reception FIFO memory): 5 channels
< UART (Asynchronous serial interface) >
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions provided
DMA transfer supported
Peripheral Functions
2
DS705-00012-1v0-E
MB91580L Series
<CSIO (Synchronous serial interface) >
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set.
Built-in dedicated baud rate generator (Master operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided.
Built-in chip selection function
DMA transfer supported
<LIN interface (v2.1)>
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
LIN protocol revision2.1 supported.
Master and slave systems supported
Framing error and overrun error detection
LIN synch break generation and detection; LIN synch delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the reload counter.
DMA transfer supported
< I
2
C >
Supported for 4 channels: ch.0,ch.1,ch.3, and ch4.
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
Standard mode (Max. 100 kbps) / high-speed mode (Max. 400 kbps) supported
DMA transfer supported (for transmission only)
CAN controller (C-CAN): 3 channels
Transfer speed: Up to 1Mbps
64-transmission/reception message buffering: 3 channels
FlexRay controller: 1unit(ch.A/ch.B)
FlexRay Specifications Version 2.1 supported
Up to 128 message buffers
8K bytes of message RAM
Variable length of message buffers
Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception
FIFO memory
Host access to the message buffer via input and output buffers
Filtering for slot counter, cycle counter and channels
Maskable interrupts are supported
PPG: 16 bits
24 channels
Reload timer: 16 bits
4 channels
A/D converter (successive approximation type)
12-bit resolution: 3units(24 channels)
Conversion time: 1 µs
Free-run timer: 16 bits
6 channels (1 channel can be selected for input capture, and 1 channel for output
compare.)
Input capture: 16 bits
8 channels (linked to the free-run timer)
Output compare: 16 bits
12 channels (linked to the free-run timer)
Waveform generator: 2 units (12 channels)
R/D converter: 1 channel (MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC)
10-bit D/A converter: 1 channel (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD)
Calibration: The hardware watchdog for CR oscillation drive
The CR oscillation frequency can be trimmed.
DS705-00012-1v0-E
3
MB91580L Series
Clock Supervisor
Anomaly supervisory feature (by damaged quartz, etc.) of external main oscillation (4MHz)
When anomaly is detected, clock is switched to CR.
Up/ down counter: 2 channels
8/16-bit Up/ down counter
Base timer: 2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can be selected and used.
A 32-bit timer can be used in 2 channels of cascade mode.
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog
NMI
Interrupt controller
Interrupt request batch read
Multiple interrupts from peripherals can be read by a series of registers.
I/O relocation
Change of pin position of peripheral functions
Low-power consumption mode
Sleep/Stop/Watch
Stop (Power shut-off)/Watch (Power shut-off)
Power-on reset
Low-voltage detection reset (external low-voltage detection)
Low-voltage detection reset (internal low-voltage detection)
Device package: LQFP-144
CMOS 90 nm technology
Power supplies
Single 5V power supply
The voltage step-down circuit brings the 5.0V down to generate 1.2V internally
I/O 5.0V
4
DS705-00012-1v0-E
MicroPython Open Source section
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