MCP37231/21-200
MCP37D31/21-200
200 Msps, 16/14-Bit Low-Power ADC with 8-Channel MUX
Features
• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/number of channels used
• SNR with f
IN
= 15 MHz and -1 dBFS:
- 74.7 dBFS (typical) at 200 Msps
• SFDR with f
IN
= 15 MHz and -1 dBFS:
- 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 490 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 390 mW at 200 Msps
• Power-Saving Modes:
- 144 mW during Standby
- 28 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 V
P-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel
Mode (Input = 15 MHz, -1 dBFS): >95 dB
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
(dual-/octal-channel modes)
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC) with I/Q or
f
S
/8 output (MCP37D31/21-200)
- Continuous wave beamforming for octal-
channel mode (MCP37D31/21-200)
• Serial Peripheral Interface (SPI)
• Auto Sync Mode to Synchronize Multiple Devices
to the Same Clock
• AEC-Q100 Qualified (Automotive Applications)
• Package Options:
(a) TFBGA-121 (8 mm x 8 mm x 1.08 mm):
- AEC-Q100 qualified
- Temperature Grade 1: -40°C to +125°C
- Includes embedded decoupling capacitors for
reference pins and bandgap output pin
(b) VTLA-124 (9 mm x 9 mm x 0.9 mm)
- Temperature Range: -40°C to +85°C
Typical Applications
•
•
•
•
•
•
Communication Instruments
Cellular Base Stations
Lidar and Radar
Ultrasound and Sonar Imaging
Scanners and Low-Power Portable Instruments
Industrial and Consumer Data Acquisition System
MCP372X1/MCP37DX1-200 Family Comparison
(1)
:
Part Number
MCP37231-200
MCP37221-200
MCP37211-200
MCP37D31-200
MCP37D21-200
MCP37D11-200
Note 1:
2:
3:
4:
Sample Rate
200 Msps
200 Msps
200 Msps
200 Msps
200 Msps
200 Msps
Resolution
16
14
12
16
14
12
Digital
CW
Digital
(2)
(3)
Down-Conversion
Beamforming
(4)
Decimation
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Noise-Shaping
Requantizer
(2)
No
No
Yes
No
No
Yes
Devices in the same package type are pin-to-pin compatible.
Available in single- and dual-channel modes.
Available in single- and dual-channel modes, and octal-channel mode when CW beamforming is enabled.
Available in octal-channel mode.
2014-2019 Microchip Technology Inc.
DS20005322E-page 1
MCP37231/21-200 AND MCP37D31/21-200
Description
The MCP37231/21-200 is Microchip's baseline 16-/14-
bit 200 Msps pipelined ADC family, featuring built-in
high-order digital decimation filters, gain and offset
adjustment per channel and fractional delay recovery.
The MCP37D31/21-200 device family features digital
down-conversion and CW beamforming capability, in
addition to the features offered by the MCP37231/21-
200.
All devices feature harmonic distortion correction and
DAC noise cancellation that enable high-performance
specifications with SNR of 74.7 dBFS (typical), and
SFDR of 90 dBc (typical).
These A/D converters exhibit industry-leading low-
power performance with only 490 mW operation while
using the LVDS interface at 200 Msps. This superior
low-power operation coupled with high dynamic
performance makes these devices ideal for various
high-performance, high-speed data acquisition
systems, including communications equipment, radar
and portable instrumentation.
The output decimation filter option improves SNR
performance up to 93.5 dBFS with the 512x decimation
setting. The digital down-conversion option, in
conjunction with the decimation and quadrature output
options, offers great flexibility in digital communication
system design, including cellular base-stations and
narrow-band communications. Gain, phase and DC
offset can be adjusted independently for each input
channel, allowing for simplified implementation of CW
beamforming and ultrasound Doppler imaging
applications.
These devices can have up to eight differential input
channels through an input MUX. The sampling rate is
up to 200 Msps when a single channel is used, or
25 Msps per channel when all eight input channels are
used.
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after 28
clock cycles of data latency. Latency will increase if any
of the digital signal post-processing (DSPP) options are
enabled.
AutoSync mode offers a great design flexibility when
multiple devices are used in applications. It allows
multiple devices to sample input synchronously at the
same clock.
The differential full-scale analog input range is
programmable up to 2.975 V
P-P
. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available as full-rate CMOS
or Double-Data-Rate (DDR) LVDS. Additionally, a
serialized LVDS option is also available for the 16-bit
octal-channel mode.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
registers.
The device is available in Pb-free TFBGA-121 and
VTLA-124 packages. The device with a TFBGA-121
Package is AEC-Q100 qualified for automotive
applications and operates over the extended
temperature range of -40°C to +125°C.
Package Types
Bottom View
Dimension:
8 mm x 8 mm x 1.08 mm
Ball Pitch:
0.65 mm
Ball Diameter:
0.4 mm
(a) TFBGA-121 Package (
AEC-Q100 Qualified).
Bottom View
Dimension:
9 mm x 9 mm x 0.9 mm
(b) VTLA-124 Package
1
.
Note 1:
Contact Microchip Technology Inc. for the
VTLA-124 Package Availability.
2014-2019 Microchip Technology Inc.
DS20005322E-page 3
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