ISL8033_11 datasheet, PDF - EEWORLD Datasheet

Dual 3A Low Quiescent Current High Efficiency

Synchronous Buck Regulator

ISL8033, ISL8033A

ISL8033 is a dual integrated power controller rated for 3A per

channel with a 1MHz step-down regulator that is ideal for any low

power low-voltage applications. The ISL8033A offers 2.5MHz

operation for smaller more compacted design. The channels are

180° out-of-phase for input RMS current and EMI reduction. It is

optimized for generating low output voltages down to 0.8V each.

The supply voltage range is from 2.85V to 6V, allowing for the use

of a single Li+ cell, three NiMH cells or a regulated 5V input. It

has a guaranteed minimum output current of 3A each when ISET

is connected to VDD. The output current of each output is

selectable by setting ISET pin.

The ISL8033, ISL8033A includes a pair of low ON-resistance

P-Channel and N-Channel internal MOSFETs to maximize

efficiency and minimize external component count. 100% duty-

cycle operation allows less than 250mV dropout voltage at 3A.

The ISL8033, ISL8033A offers an independent 1ms Power-Good

(PG) timer at power-up. When shutdown, ISL8033, ISL8033A

discharges the output capacitor. Other features include internal

digital soft-start, enable for power sequence, controllable soft-

stop output discharge during disabled, start-up with pre-biased

output, 100% maximum duty cycle for lowest dropout, 100%

duty cycle operation for smooth transition, less than 8µA logic

controlled shutdown current, independent enable, overcurrent

protection, and thermal shutdown.

The ISL8033, ISL8033A is offered in a 24 Ld 4mmx4mm QFN

package with 1mm maximum height. The complete converter

occupies less than 5.46cm

2

area.

Features

• Dual 3A High Efficiency Synchronous Buck Regulator with up

to 95% Efficiency

• 2% Output Accuracy Over-Temperature/Load/Line

• Internal Digital Soft-Start - 1.5ms

• External Synchronization up to 6MHz (ISL8033)

• Internal Current Mode Compensation

• Peak Current Limiting and Hiccup Mode Short Circuit

Protection

• Adjustable Peak Overload Current

• Negative Current Protection

• Pb-Free (RoHS Compliant)

Applications

• DC/DC POL Modules

• µC/µP, FPGA and DSP Power

• Plug-in DC/DC Modules for Routers and Switchers

• Test and Measurement Systems

• Li-ion Battery Power Devices

• Bar Code Readers

Related Literature

• See

AN1606,

ISL8033EVAL1Z Application Note

• See

AN1611,

ISL8033EVAL2Z Application Note

100

90

EFFICIENCY (%)

80

70

60

50

40

0.0

V

IN

= 5V

0.5

1.0

1.5

I

OUT

(A)

2.0

2.5

3.0

3.3V

OUT

FIGURE 1. EFFICIENCY vs LOAD

March 24, 2011

FN6854.2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL8033, ISL8033A

Typical Application Circuit

INPUT 2.85V TO 6V

VIN1, 2

LX1

C2

2x22µF

PGND

ISET

EN1

ISL8033

FB1

R3

100k

SGND

SYNC

LX2

EN2

PGND

PG2

FB2

R6

100k

SGND

R5

124k

C4

2x22µF

C5

12pF

L2

1.5µH

OUTPUT2

1.8V/3A

R2

124k

C3

12pF

L1

1.5µH

OUTPUT1

1.8V/3A

C1

2x22µF

VDD

PG1

FIGURE 2. TYPICAL APPLICATION DIAGRAM - DUAL INDEPENDENT OUTPUTS

TABLE 1. ISL8033 COMPONENT VALUE SELECTION

V

OUT

C1

C2 (or C4)

C3 (or C5)

L1 (or L2)

R2 (or R5)

R3 (or R6)

0.8V

2x22µF

12pF

1.0µH~2.2µH

0

100k

1.2V

2x22µF

12pF

1.0µH~2.2µH

50k

100k

1.5V

2x22µF

12pF

1.0µH~2.2µH

87.5k

100k

1.8V

2x22µF

12pF

1.0µH~3.3µH

124k

100k

2.5V

2x22µF

12pF

1.0µH~3.3µH

212.5k

100k

3.3V

2x22µF

12pF

1.0µH~4.7µH

312.5k

100k

TABLE 2. ISL8033A COMPONENT VALUE SELECTION

V

OUT

C1

C2 (or C4)

C3 (or C5)

L1 (or L2)

R2 (or R5)

R3 (or R6)

0.8V

2x22µF

12pF

0.47~1.5µH

0

100k

1.2V

2x22µF

12pF

0.47~1.5µH

50k

100k

1.5V

2x22µF

12pF

0.47~1.5µH

87.5k

100k

1.8V

2x22µF

12pF

0.47~1.5µH

124k

100k

2.5V

2x22µF

12pF

1.0~2.2µH

212.5k

100k

3.3V

2x22µF

12pF

1.0~3.3µH

312.5k

100k

NOTE: The minimum output capacitor value is given for different output voltage to make sure the whole converter system is stable. Output capacitance

should increase to support faster load transient requirement.

TABLE 3. SUMMARY OF DIFFERENCES

PART NUMBER

ISL8033

ISL8033A

Internally fixed switching frequency F

SW

= 1MHz

Internally fixed switching frequency F

SW

= 2.5MHz

SWITCHING FREQUENCY

2

FN6854.2

March 24, 2011

ISL8033, ISL8033A

Block Diagram

27pF

SO FT-

S TA R T

SH U TD O W N

+

EN 1

B A N D G A P 0.8V

390k

0.3pF

S H U TD O W N

V IN

EA M P

+

COMP

PW M

LO G IC

C O N TR O LLER

PR O TEC TIO N

D R IV E R

LX1

3pF

SLO P E

COMP

FB 1

1.6k

0.5V

SC P

+

PGND

+

CSA1

0.864V

+

V IN

1M

PG1

SGND

O S C ILLA TO R

0.736V

1m s

D E LA Y

SYNC

TH ER M A L

S H U TD O W N

OCP

TH R E S H O LD

LO G IC

IS ET

SO FT-

STA

S TAT T

RR

S H U TD O W N

+

EN 2

B A N D G A P 0.8V

27pF

390k

0.3pF

S H U TD O W N

V IN

EAM P

+

COMP

3pF

SLO P E

COMP

FB 2

1.6k

0.5V

SCP

+

PW M

LO G IC

C O N TR O LLE R

P R O TEC TIO N

D R IV E R

LX2

PGND

+

CSA2

0.864V

+

V IN

0.736V

1M

PG2

SGND

1m s

D E LA Y

3

FN6854.2

March 24, 2011

ISL8033, ISL8033A

Pin Configuration

ISL8033, ISL8033A

(24 LD QFN)

TOP VIEW

PGND2

PGND1

LX2

24

LX2

VIN2

EN2

PG2

FB2

1

2

3

4

5

6

7

NC

23

22

21

20

19

18 LX1

17 VIN1

LX1

25

PD

16 VIN1

15 VDD

14 ISET

13 EN1

8

NC

9

FB1

10

SGND

11

PG1

12

SYNC

Pin Descriptions

PIN NUMBER

1, 24

22, 23

4

5

6

SYMBOL

LX2

PGND2

EN2

PG2

FB2

DESCRIPTION

Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.

Negative supply for the power stage of Channel 2.

Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and

discharge output capacitor when driven to low. Do not leave this pin floating.

1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT2 voltage.

The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier.

The output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output

voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. There

is an internal compensation to meet a typical application.

In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2

regulator output voltage.

No connect pins. Please tie to GROUND.

The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error

amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly selected

divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the

0.8V reference. There is an internal compensation to meet a typical application.

In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1

regulator output voltage.

System ground. Make a single point connection from these pins to PGND.

1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT1 voltage.

Connect to logic high or input voltage VIN. Connect to an external function generator for external Synchronization.

Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).

Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and

discharge output capacitor when driven to low. Do not leave this pin floating.

ISET is the output current limit setting of the regulators. See the “” table on page 6 for settings.

Input supply voltage for the logic. Connect VIN pin.

Negative supply for the power stage of Channel 1.

7, 8

9

NC

FB1

10

11

12

13

14

15

20, 21

SGND

PG1

SYNC

EN1

ISET

VDD

PGND1

4

FN6854.2

March 24, 2011

ISL8033, ISL8033A

Pin Descriptions

(Continued)

PIN NUMBER

18, 19

2, 3,

16, 17

25

SYMBOL

LX1

VIN2,

VIN1

PD

DESCRIPTION

Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.

Input supply voltage. Connect a 22µF ceramic capacitor to power-ground per channel.

The exposed pad must be connected to the PGND pin for proper electrical performance. Add as much vias as

possible under this pad for optimal thermal performance.

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

ISL8033IRZ*

ISL8033AIRZ*

NOTES:

1. Add “-T*” suffix for tape and reel.Please refer to

TB347

for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for

ISL8033, ISL8033A.

For more information on MSL, please see Technical

Brief

TB363.

PART

MARKING

80 33IRZ

80 33AIRZ

TEMP. RANGE

(°C)

-40 to +85

PACKAGE

(Pb-free)

24 Ld 4x4 QFN

PKG.

DWG. #

L24.4x4D

5

FN6854.2

March 24, 2011

ISL8033_11

ISL8033_11 Overview

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