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EPM7064STC100-7N

Description
EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,66 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Environmental Compliance
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EPM7064STC100-7N Overview

EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100

EPM7064STC100-7N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIntel
package instructionLFQFP, TQFP100,.63SQ
Reach Compliance Codecompliant
ECCN codeEAR99
Other features64 MACROCELLS; 4 LABS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency166.7 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G100
JESD-609 codee3
JTAG BSTNO
length14 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines68
Number of macro cells64
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 68 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeTQFP100,.63SQ
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3/5,5 V
Programmable logic typeEE PLD
propagation delay7.5 ns
Certification statusNot Qualified
Maximum seat height1.27 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width14 mm

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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