Active Delay Line, 4-Func, 1-Tap, True Output, CMOS, 0.300 INCH HEIGHT, DIP-16/12
| Parameter Name | Attribute value |
| Is it lead-free? | Contains lead |
| Is it Rohs certified? | incompatible |
| Maker | Engineered Components Co. |
| Parts packaging code | DIP |
| package instruction | QIP, DIP16,.3 |
| Contacts | 16/12 |
| Reach Compliance Code | unknown |
| Other features | MAX FAN OUT OF 10 TTL LOAD PER OUTPUT; INTERNAL TERMINATION; MAX RISE TIME CAPTURED |
| series | ACT |
| JESD-30 code | R-XDIP-P12 |
| JESD-609 code | e0 |
| length | 22.86 mm |
| Logic integrated circuit type | ACTIVE DELAY LINE |
| Number of functions | 4 |
| Number of taps/steps | 1 |
| Number of terminals | 12 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| Output polarity | TRUE |
| Package body material | UNSPECIFIED |
| encapsulated code | QIP |
| Encapsulate equivalent code | DIP16,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| programmable delay line | NO |
| Prop。Delay @ Nom-Sup | 18 ns |
| Certification status | Not Qualified |
| Maximum seat height | 7.62 mm |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | PIN/PEG |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| Total delay nominal (td) | 18 ns |
| width | 7.62 mm |
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