and is a member of the HiperClockS™ family of high
HiPerClockS™
performance clock solutions from IDT. The device
provides five banks of outputs and a reference clock.
The banks can be enabled by using a common output
enable pin. A 25MHz crystal is used to generate the 50MHz,
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz
frequencies.
F
EATURES
•
Five banks of outputs:
Bank A:
one single-ended (QA0) LVCMOS output at: 133MHz
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz
and 125MHz
Bank B:
two (QB0, QB1) LVCMOS outputs at: 50MHz
Bank C:
one (QC0/nQC0) differential LVPECL output at: 87.5MHz
Bank D:
one (QD0/nQD0) differential LVDS output at: 350MHz
One single-ended LVCMOS reference clock output at: 25MHz
•
Crystal input frequency: 25MHz
V
CCO
_
LVCMOS
IC
S
P
IN
A
SSIGNMENT
V
CCO
_
LVCMOS
REF_OUT
QB0
QB1
QA0
V
EE
V
EE
•
Maximum output frequency: 350MHz
•
±5% frequency margining
•
Full 3.3V operating supply
•
0°C to 70°C ambient operating temperature
24
V
CC
QA1
nQA1
V
CCA
1
V
EE
QC0
nQC0
V
CC
LVCMOS - 133MHz
32 31 30 29 28 27 26 25
F_SEL0
F_SEL1
V
CC
XTAL_IN
XTAL_OUT
V
EE
V
CCA
2
RESET
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MARGIN_MODE
PLL_BYPASS
MARGIN
OE
QD0
V
EE
nQD0
V
CC
•
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
ICS843S2807
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
23
22
21
20
19
18
17
B
LOCK
D
IAGRAM
LVCMOS - 25MHz
REF_OUT
÷5.2631
F_SEL[1:0]
Pullup
PLL_BYPASS
Pulldown
2
QA0
1
25MHz
LVPECL - 66.67/100/
125MHz
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
700MHz
0
÷5.6,
÷7,
÷10.5
QA1
nQA1
LVCMOS - 50MHz
QB0
÷28
±5%
Frequency
Margining
÷14
QB1
LVPECL - 87.5MHz
QC0
÷8
nQC0
LVDS - 350MHz
QD0
MARGIN
Pulldown
MARGIN_MODE
Pulldown
RESET
Pulldown
OE
Pullup
÷2
nQD0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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