8:1, SINGLE-ENDED MULTIPLEXER
ICS83058I
G
ENERAL
D
ESCRIPTION
The ICS83058I is a low skew, 8:1, Single-ended
Multiplexer and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS83058I has eight selectable single-
ended clock inputs and one single-ended clock
output. The output has a V
DDO
pin which may be set at 3.3V,
2.5V, or 1.8V, making the device ideal for use in voltage trans-
lation applications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug purposes. The device operates up to 250MHz and is
packaged in a 16 TSSOP package.
F
EATURES
• 8:1 single-ended multiplexer
• Q nominal output impedance: 7Ω (V
DDO
= 3.3V)
•
Maximum output frequency: 250MHz
IC
S
• Propagation delay: 3ns (maximum), V
DD
= V
DDO
= 3.3V
• Input skew: 225ps (maximum), V
DD
= V
DDO
= 3.3V
•
•
Part-to-part skew: 475ps (maximum), V
DD
= V
DDO
= 3.3V
Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
•
-40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
SEL2
SEL1
SEL0
OE
Q
P
IN
A
SSIGNMENT
Q
CLK7
OE
CLK6
GND
CLK5
SEL2
CLK4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DDO
CLK0
SEL0
CLK1
V
DD
CLK2
SEL1
CLK3
ICS83058I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
IDT
™
/ ICS
™
8:1, SINGLE-ENDED MULTIPLEXER
1
ICS83058AGI REV. C MARCH 10, 2008
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 4, 6,
8, 9, 11,
13, 15
3
5
7, 10, 14
12
16
Name
Q
CLK7, CLK6, CLK5,
CLK4, CLK3, CLK2,
CLK1, CLK0
OE
GND
SEL2, SEL1, SEL0
V
DD
V
DDO
Type
Output
Input
Input
Power
Input
Power
Power
Description
Single-ended clock output. LVCMOS/LVTTL interface levels.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Power supply ground.
Clock select input. See Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
Core and input supply pin.
Pullup
Output supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 1.89V
V
DDO
= 3.465V
R
OUT
Output Impedance
V
DDO
= 2.625V
V
DDO
= 1.89V
Test Conditions
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
SEL2
0
0
0
0
1
1
1
1
Control Inputs
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
IDT
™
/ ICS
™
8:1, SINGLE-ENDED MULTIPLEXER
2
ICS83058AGI REV. C MARCH 10, 2008
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
89°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
40
5
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
40
5
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.71
Typical
3.3
1.8
Maximum
3.465
1.89
40
5
Units
V
V
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
35
5
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.71
Typical
2.5
1.8
Maximum
2.625
1.89
35
5
Units
V
V
mA
mA
IDT
™
/ ICS
™
8:1, SINGLE-ENDED MULTIPLEXER
3
ICS83058AGI REV. C MARCH 10, 2008
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK0:CLK5,
SEL0:SEL2
OE
CLK0:CLK5,
SEL0:SEL2
OE
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output HighVoltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
-5
-150
2.6
1.8
V
DD
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
Input High Current
I
IL
Input Low Current
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
Par t-to-Par t Skew; NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
1.8
2.5
2.4
2.7
55
155.52MHz,
(12kHz to 20MHz)
0.19
475
20% to 80%
50
45
500
55
Test Conditions
Minimum
Typical
Maximum
250
3.0
2.9
225
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
t
sk(i)
t
jit
t
sk(pp)
t
R
/ t
F
odc
MUX
ISOL
MUX Isolation
@ 100MHz
45
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
IDT
™
/ ICS
™
8:1, SINGLE-ENDED MULTIPLEXER
4
ICS83058AGI REV. C MARCH 10, 2008
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
Par t-to-Par t Skew; NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
2.0
2.6
2.5
2.8
45
155.52MHz,
(12kHz to 20MHz)
0.14
400
20% to 80%
50
45
500
55
Test Conditions
Minimum
Typical
Maximum
250
3.1
3.0
150
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
t
sk(i)
t
jit
t
sk(pp)
t
R
/ t
F
odc
MUX
ISOL
MUX Isolation
@ 100MHz
45
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 3
Par t-to-Par t Skew; NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
2.3
2.8
2.9
3.3
50
155.52MHz,
(12kHz to 20MHz)
0.16
475
20% to 80%
100
45
700
55
Test Conditions
Minimum
Typical
Maximum
250
3.8
3.8
150
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
t
sk(i)
t
jit
t
sk(pp)
t
R
/ t
F
odc
MUX
ISOL
MUX Isolation
@ 100MHz
45
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
IDT
™
/ ICS
™
8:1, SINGLE-ENDED MULTIPLEXER
5
ICS83058AGI REV. C MARCH 10, 2008
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