Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MMA52xxAKW
Rev. 0, 09/2012
Xtrinsic MMA52xxAKW
PSI5 Inertial Sensor
The MMA52xxAKW family, a SafeAssure solution, includes the PSI5 Version 1.3
asynchronous mode compatible overdamped X-axis satellite accelerometers.
Features
±60g to ±480g Full-Scale Range
400 Hz, 3-Pole Low-Pass Filter
Single Pole, High-Pass Filter with Fast Startup and Output Rate Limiting
PSI5 Version 1.3 Asynchronous Mode Compatible
– PSI5-A10P-228/1L Compatible
– Baud Rate: 125 kBaud
– 10-bit Data
– Even Parity Error Detection
• 16
μs
Internal Sample Rate, with Interpolation to 1
μs
• Pb-Free 16-Pin QFN, 6 by 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
Typical Applications
• Airbag Front and Side Crash Detection
•
•
•
•
MMA52xxAKW
Bottom View
16-PIN QFN
CASE 2086-01
Top View
TEST
V
SSA
16 15 14 13
V
CC
1
V
SS
2
I
DATA
3
Shipping
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
V
BUF
12 V
SSA
11 V
REGA
10 CS
9 V
REG
8
D
IN
17
ORDERING INFORMATION
Device
MMA5206AKW
MMA5212AKW
MMA5224AKW
MMA5248AKW
MMA5206AKWR2
MMA5212AKWR2
MMA5224AKWR2
MMA5248AKWR2
Axis
X
X
X
X
X
X
X
X
Range
60g
120g
240g
480g
60g
120g
240g
480g
Package
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
V
SS
4
5
NC
6
SLCK
7
D
OUT
PIN CONNECTIONS
© 2012 Freescale Semiconductor, Inc. All rights reserved.
NC
Application Diagram
VV
BUF
V
BUF
V
REG
V
REGA
C4
C5
C6
V
CC
I
DATA
R1
R2
C2
C3
C1
V
CE
MMA51xx
V
SSA
V
SS
CS
SCLK
DO
V
SS
Note: Pin names and references
may differ from PSI5 V1.3
pin names and references
DI
Figure 1. Application Diagram
External Component Recommendations
Ref Des
C1
C3
C2
C4, C5, C6
R1
R2
Type
Ceramic
Ceramic
Ceramic
Ceramic
General Purpose
General Purpose
Description
2.2 nF, 10%, 50V minimum, X7R
470 pF, 10%, 50V minimum, X7R
15 nF, 10%, 50V minimum, X7R
1
μF,
10%, 10V minimum, X7R
82Ω, 5%, 200 PPM
27Ω, 5%, 200 PPM
Purpose
V
CC
Power Supply Decoupling and Signal Damping
I
DATA
Filtering and Signal Damping
V
CC
Power Supply Decoupling
Voltage Regulator Output Capacitor(s)
V
CC
Filtering and Signal Damping
I
DATA
Filtering and Signal Damping
Device Orientation
xxxxxxx
xxxxxxx
X: 0g
MMA52xxAKW
2
Sensors
Freescale Semiconductor, Inc.
xxxxxxx
xxxxxxx
X: +1g
Figure 2. Device Orientation Diagram
xxxxxxx
xxxxxxx
X: 0g
xxxxxxx
xxxxxxx
X: -1g
X: 0g
X: 0g
EARTH GROUND
Internal Block Diagram
V
CC
Buffer
Voltage
Regulator
Reference
Voltage
V
BUF
Digital
Voltage
Regulator
Analog
Voltage
Regulator
V
BUF
V
REG
V
REG
V
REF
V
REGA
V
BUF
V
REGA
V
SSA
CS
SCLK
D
IN
D
OUT
Control
Logic
SPI
Low Voltage
Detection
Sync Pulse
Detection
Programming
Interface
V
CC
OTP
Array
I
DATA
Serial
Encoder
V
SS
V
REG
Self-Test
Interface
Control
In
Status
Out
DSP
ΣΔ
Converter
V
REGA
g-cell
V
REG
Offset
Monitor
HPF
SINC Filter
IIR
LPF
Compensation
Figure 3. Block Diagram
MMA52xxAKW
Sensors
Freescale Semiconductor, Inc.
3
1
Pin Connections
TEST
V
SSA
V
BUF
12 V
SSA
11 V
REGA
10 CS
9 V
REG
5
NC
6
SLCK
7
D
OUT
8
D
IN
Definition
This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capac-
itor must be connected between this pin and V
SS
. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 com-
munication. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
This pin must be left unconnected in the application.
This input pin provides the serial clock to the SPI port for test purposes. An internal pulldown device is connected to this pin.
This pin must be grounded or left unconnected in the application.
This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the appli-
cation.
This pin functions as the serial data input to the SPI port for test purposes. An internal pulldown device is connected to this
pin. This pin must be grounded or left unconnected in the application.
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
this pin and V
SS
. Reference
Figure 1.
This input pin provides the chip select to the SPI port for test purposes. An internal pullup device is connected to this pin.This
pin must be left unconnected in the application.
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between
this pin and V
SSA
. Reference
Figure 1.
This pin is the power supply return node for the analog circuitry.
This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies both the analog (V
REGA
) and
digital (V
REG
) supplies to provide immunity from EMC and supply dropouts on V
CC
. An external capacitor must be connected
between this pin and V
SS
. Reference
Figure 1.
This pin is must be grounded or left unconnected in the application.
This pin must be left unconnected in the application.
This pin is the power supply return node for the analog circuitry.
This pin is the die attach flag, and is internally connected to VSS.
The corner pads are internally connected to V
SS
.
16 15 14 13
V
CC
1
V
SS
2
I
DATA
3
V
SS
4
17
Figure 4. Top View, 16-Pin QFN Package
Table 1. Pin Description
Pin
1
2
3
4
5
6
Pin
Name
V
CC
V
SS
I
DATA
V
SS
NC
SCLK
Formal Name
Supply
Digital GND
Response
Current
Digital GND
Not Connected
SPI Clock
7
D
OUT
D
IN
V
REG
CS
SPI Data Out
8
SPI Data In
Digital
Supply
Chip Select
Analog
Supply
Analog GND
Power
Supply
Test Pin
Not Connected
Analog GND
Die Attach Pad
Corner Pads
9
10
11
12
V
REGA
VSSA
13
V
BUF
TEST
NC
VSSA
PAD
Corner
Pads
14
15
16
17
MMA52xxAKW
4
Sensors
Freescale Semiconductor, Inc.
NC
2
2.1
#
1
2
3
4
5
6
7
8
Electrical Characteristics
Maximum Ratings
Rating
Supply Voltage (V
CC
, I
DATA
)
Reverse Current
≤
160 mA, t
≤
80 ms
Continuous
Transient (< 10
μs)
V
BUF,
Test
V
REG
, V
REGA
,
SCLK, CS, D
IN
, D
OUT
Powered Shock (six sides, 0.5 ms duration)
Unpowered Shock (six sides, 0.5 ms duration)
Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation)
Electrostatic Discharge (per AECQ100)
External Pins (V
CC
, I
DATA
, V
SS
, V
SSA
), HBM (100 pF, 1.5 kΩ)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0Ω)
MM (200 pF, 0Ω)
Temperature Range
Storage
Junction
Thermal Resistance
g
pms
g
shock
h
DROP
V
ESD
V
ESD
V
ESD
V
ESD
T
stg
T
J
θ
JC
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
Symbol
V
CC_REV
V
CC_MAX
V
CC_TRANS
Value
-0.7
+20.0
+25.0
-0.3 to +4.2
-0.3 to +3.0
±2000
±2500
1.2
±4000
±2000
±1500
±200
-40 to +125
-40 to +150
2.5
Unit
V
V
V
V
V
g
g
m
(3)
(3)
(9)
(3)
(3)
(3)
(3)
(5)
9
10
11
12
V
V
V
V
(5)
(5)
(5)
(5)
13
14
15
°C
°C
°C/W
(3)
(9)
(9, 14)
2.2
#
16
17
18
19
Operating Range
Characteristic
Supply Voltage
V
L
≤
(V
CC
- V
SS
)
≤
V
H
, T
L
≤
T
A
≤
T
H
,
ΔT ≤
25 K/min, unless otherwise specified.
Symbol
V
CC
V
CC_UV
Operating Temperature Range
T
A
T
A
Min
V
L
4.2
V
VCC_UV_F
T
L
-40
-40
Typ
—
—
⎯
⎯
Max
V
H
17.0
V
L
T
H
+105
+125
Units
V
V
(1)
(9)
°C
°C
(1)
(3)
MMA52xxAKW
Sensors
Freescale Semiconductor, Inc.
5
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