ST72521M/R/AR
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
FIVE TIMERS, SPI, SCI, I
2
C, CAN INTERFACE
DATA BRIEFING
s
s
s
s
s
Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
Cloc anced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal or external RC oscillator,
clock security system and bypass for external
clock
– PLL for 2x frequency multiplication
– Four power saving modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– TLI dedicated top level interrupt pin
– 15 external interrupt lines (on 4 vectors)
Up to 64 I/O Ports
– 48 multifunctional bidirectional I/O lines
– 34 alternate function lines
– 16 high sink outputs
5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
and time base interrupt, external clock with
event detector
Features
ST72(F)521(M/R/AR)9
TQFP64
14 x 14
TQFP80
14 x 14
TQFP64
10 x 10
s
s
4 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN com-
patible)
– I
2
C multimaster interface
– CAN interface (2.0B Passive)
Analog peripheral
– 10-bit ADC with 16 input pins
Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
– True Bit Manipulation
Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
ST72(F)521(R/AR)6
s
s
Device Summary
ST72521(M/R/AR)7
Program memory - bytes
60K
48K
32K
RAM (stack) - bytes
2048 (256)
1536 (256)
1024 (256)
Operating Voltage
3.8V to 5.5V
Temp. Range (ROM)
0°C to 70°C / -10°C to +85
°C
/ -40°C to +85
°C
/ -40°C to +105°C / -40°C to +125°C
Temp. Range (Flash)
-40°C to +85
°C
/ -40°C to +125°C
N/A
-40°C to +125
°C
Package
TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR)
TQFP64 14x14 (R), TQFP64 10x10 (AR)
Rev. 1.5
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/11
1
ST72521M/R/AR
1 INTRODUCTION
The ST72521(A)R and ST72521M devices are
members of the ST7 microcontroller family de-
signed for mid-range applications with a CAN bus
interface (Controller Area Network).
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
RESET
V
PP
TLI
V
SS
V
DD
EVD
OSC1
OSC2
CONTROL
RAM
(1024-2048 Bytes)
LVD
AVD
OSC
I2C
PORT A
PORT B
PB7:0
(8-bits)
PWM ART
PORT C
TIMER B
CAN
SPI
SCI
PORT D
PD7:0
(8-bits)
10-BIT ADC
V
AREF
V
SSA
1
On
PROGRAM
MEMORY
(32K - 60K Bytes)
WATCHDOG
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PA7:0
(8-bits)
PORT F
PF7:0
(8-bits)
TIMER A
BEEP
PORT E
PE7:0
(8-bits)
PC7:0
(8-bits)
PORT G
1
PORT H
1
PG7:0
(8-bits)
PH7:0
(8-bits)
some devices only, see Device Summary on page 1
2/11
ST72521M/R/AR
PIN DESCRIPTION
(Cont’d)
Legend / Abbreviations for
Table 1:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3V
DD
/0.7V
DD
C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
T
T
= TTL 0.8V / 2V with Schmitt trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt
1)
, ana = analog
– Output:
OD = open drain
2)
, PP = push-pull
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
TQFP80
TQFP64
Type
Pin Name
Level
Output
Input
Port
Input
float
wpu
ana
int
Main
Output function
(after
reset)
OD
X
X
X
X
ei
2
ei
2
ei
2
Alternate function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
-
-
-
-
9
10
11
12
13
14
15
16
-
-
17
18
19
20
PE4 (HS)
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0/PWM3
PB1/PWM2
PB2/PWM1
PB3/PWM0
PG0
PG1
PG2
PG3
PB4 (HS)/ARTCLK
PB5/ARTIC1
PB6/ARTIC2
PB7
PD0 /AIN0
PD1/AIN1
PD2/AIN2
PD3/AIN3
PG6
PG7
PD4/AIN4
PD5/AIN5
PD6/AIN6
PD7/AIN7
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O T
T
I/O T
T
I/O T
T
I/O T
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O T
T
I/O T
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
HS
HS
HS
HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
Port B0
Port B1
Port B2
Port B3
Port G0
Port G1
Port G2
Port G3
Port B4
Port B5
Port B6
Port B7
Port D0
Port D1
Port D2
Port D3
Port G6
Port G7
Port D4
Port D5
Port D6
Port D7
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
PWM-ART External Clock
PWM-ART Input Capture 1
PWM-ART Input Capture 2
PWM Output 3
PWM Output 2
PWM Output 1
PWM Output 0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ei2
X
X
X
X
ei3
ei3
ei3
ei3
X
X
X
X
X
X
X
X
X
X
HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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