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Datasheet> All Categories > storage> storage> K6F2016V4E-EF700
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K6F2016V4E-EF700

Description
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48
Categorystorage    storage   
File Size158KB，9 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
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K6F2016V4E-EF700 Overview

Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48

K6F2016V4E-EF700 Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeBGA
package instructionVFBGA,
Contacts48
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time70 ns
JESD-30 codeR-PBGA-B48
length7 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals48
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
width6 mm

K6F2016V4E-EF700 Preview

K6F2016V4E Family
Document Title
CMOS SRAM
128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0
1.0
Initial Draft
Finalize
Draft Date
November 27, 2001
March 8, 2002
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 1.0
March 2002
K6F2016V4E Family
FEATURES
•
•
•
•
•
•
CMOS SRAM
GENERAL DESCRIPTION
The K6F2016V4E families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with
low data retention current.
128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Process Technology: Full CMOS
Organization: 128K x16 bit
Power Supply Voltage: 3.0~3.6V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
0.5µA
2)
Operating
(I
CC1
, Max)
4mA
PKG Type
K6F2016V4E-F
Industrial(-40~85°C)
3.0~3.6V
55
1)
/70ns
48-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
CC
=3.3V, T
A
=25°C and not 100% tested.
PIN DESCRIPTION
1
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A
LB
OE
A0
A1
A2
DNU
Vcc
Vss
B
I/O9
UB
A3
A4
CS1
I/O1
Row
Addresses
C
I/O10
I/O11
A5
A6
I/O2
I/O3
Row
select
Memory array
1024 rows
128
×
16 columns
D
Vss
I/O12
DNU
A7
I/O4
Vcc
E
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
F
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O
9
~I/O
16
G
I/O16
DNU
A12
A13
WE
I/O8
Column Addresses
H
DNU
A8
A9
A10
A11
DNU
48-TBGA: Top View (Ball Down)
Name
Function
Name
Vcc
Vss
UB
LB
DNU
Function
Power
Ground
Upper Byte(I/O
9
~
16
)
Lower Byte(I/O
1
~
8
)
Do Not Use
CS
OE
WE
UB
LB
Control Logic
CS
1
, CS
2
Chip Select Inputs
OE
WE
A
0
~A
16
Output Enable Input
Write Enable Input
Address Inputs
I/O
1
~I/O
16
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice
.
-2-
Revision 1.0
March 2002
K6F2016V4E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F2016V4E-EF55
K6F2016V4E-EF70
Function
CMOS SRAM
48-TBGA, 55ns, 3.3V
48-TBGA, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS
H
X
1)
L
L
L
L
L
L
L
L
OE
X
1)
X
1)
H
H
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
X
1)
H
H
H
H
H
L
L
L
LB
X
1)
H
L
X
1)
L
H
L
L
H
L
UB
X
1)
H
X
1)
L
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don′t care.(Must be low or high state.)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to V
CC
+0.3V
-0.2 to 4.0V
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability.
-3-
Revision 1.0
March 2002
K6F2016V4E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Note:
1. T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width
≤20ns.
3. Undershoot: -2.0V in case of pulse width
≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol
Vcc
Vss
V
IH
V
IL
Min
3.0
0
2.2
-0.2
3)
Typ
3.3
0
-
-
Max
3.6
0
Vcc+0.2
2)
0.6
Unit
V
V
V
V
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Symbol
I
LI
I
LO
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current (CMOS)
V
OL
V
OH
I
SB1
Cycle time=Min, I
IO
=0mA, 100% duty, CS=V
IL
,
LB=V
IL
or/and UB=V
IL
, V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
Other input =0~Vcc
1) CS≥Vcc-0.2V(CS controlled) or
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)
-
-
2.4
-
-
-
-
0.5
40
0.4
-
10
mA
V
V
µA
V
IN
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
Cycle time=1µs, 100%duty, I
IO
=0mA, CS≤0.2V,
LB≤0.2V or/and UB≤0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Test Conditions
Min
-1
-1
-
Typ
1)
-
-
-
Max
1
1
4
Unit
µA
µA
mA
1. Typical values are measured at V
CC
=3.3V, T
A
=25°C and not 100% tested.
-4-
Revision 1.0
March 2002
K6F2016V4E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=3.0~3.6V, Industrial product:T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Read
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
UB, LB Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
1. The parameter is measured with 30pF test load.
55ns
1)
Max
-
55
55
25
55
-
-
-
20
20
20
-
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
-
10
10
5
0
0
0
10
70
60
0
60
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
70
-
-
-
25
25
25
-
-
-
-
-
-
-
-
20
-
-
-
Units
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
-
10
10
5
0
0
0
10
55
45
0
45
45
40
0
0
25
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
1)
Vcc= 1.5V, CS≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
tRC
Typ
2)
-
0.5
-
-
Max
3.6
2
-
-
Unit
V
µA
ns
1. 1) CS≥Vcc-0.2V(CS controlled) or
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)
2. Typical values are measured at T
A
=25°C and not 100% tested.
-5-
Revision 1.0
March 2002
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

K6F2016V4E-EF700 Related Products

K6F2016V4E-EF700 K6F2016V4E-EF550
Description Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48 Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TBGA-48
Maker SAMSUNG SAMSUNG
Parts packaging code BGA BGA
package instruction VFBGA, VFBGA,
Contacts 48 48
Reach Compliance Code unknown unknown
ECCN code 3A991.B.2.A 3A991.B.2.A
Maximum access time 70 ns 55 ns
JESD-30 code R-PBGA-B48 R-PBGA-B48
length 7 mm 7 mm
memory density 2097152 bit 2097152 bit
Memory IC Type STANDARD SRAM STANDARD SRAM
memory width 16 16
Number of functions 1 1
Number of terminals 48 48
word count 131072 words 131072 words
character code 128000 128000
Operating mode ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
organize 128KX16 128KX16
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VFBGA VFBGA
Package shape RECTANGULAR RECTANGULAR
Package form GRID ARRAY, VERY THIN PROFILE, FINE PITCH GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial PARALLEL PARALLEL
Certification status Not Qualified Not Qualified
Maximum seat height 1 mm 1 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal form BALL BALL
Terminal pitch 0.75 mm 0.75 mm
Terminal location BOTTOM BOTTOM
width 6 mm 6 mm

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