M36W0R6050T0ZAQ datasheet, PDF

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M36W0R6050T0ZAQ: DescriptionSPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88; Categorystorage storage; File Size404KB，17 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M36W0R6050T0ZAQ Overview

SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88

M36W0R6050T0ZAQ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	8 X 10 MM, 0.80 MM PITCH, TFBGA-88
Contacts	88
Reach Compliance Code	not_compliant
Maximum access time	85 ns
Other features	PSRAM IS ORGANIZED AS 2M X 16
JESD-30 code	R-PBGA-B88
JESD-609 code	e0
length	10 mm
memory density	67108864 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+PSRAM
Number of functions	1
Number of terminals	88
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA88,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.0001 A
Maximum slew rate	0.045 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

M36W0R6050T0ZAQ Preview

M36W0R6050T0

M36W0R6050B0

64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory

and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package

FEATURES SUMMARY

MULTI-CHIP PACKAGE

– 1 die of 64 Mbit (4Mb x 16) Flash Memory

– 1 die of 32 Mbit (2Mb x 16) Pseudo SRAM

■

SUPPLY VOLTAGE

– V

DDF

= V

CCP

= V

DDQ

= 1.7V to 1.95V

■

LOW POWER CONSUMPTION

■

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code (Top Flash Configuration),

M36W0R6050T0: 8810h

– Device Code (Bottom Flash

Configuration), M36W0R6050B0: 8811h

■

PACKAGE

– Compliant with Lead-Free Soldering

Processes

– Lead-Free Versions

FLASH MEMORY

■

PROGRAMMING TIME

– 8µs by Word typical for Fast Factory

Program

– Double/Quadruple Word Program option

– Enhanced Factory Program options

■

MEMORY BLOCKS

– Multiple Bank Memory Array: 4 Mbit

Banks

– Parameter Blocks (Top location)

■

SYNCHRONOUS / ASYNCHRONOUS READ

– Synchronous Burst Read mode: 66MHz

– Asynchronous/ Synchronous Page Read

mode

– Random Access: 70ns

■

DUAL OPERATIONS

– Program Erase in one Bank while Read in

others

– No delay between Read and Write

operations

■

BLOCK LOCKING

– All blocks locked at Power-up

– Any combination of blocks can be locked

– WP

for Block Lock-Down

■

Figure 1. Package

FBGA

Stacked TFBGA88 (ZAQ)

8 x 10mm

-O

■

SECURITY

– 128-bit user programmable OTP cells

– 64-bit unique device number

■

COMMON FLASH INTERFACE (CFI)

■

100,000 PROGRAM/ERASE CYCLES per

BLOCK

PSRAM

■

ACCESS TIMES: 85ns

■

LOW STANDBY CURRENT: 100µA

■

DEEP POWER DOWN CURRENT: 10µA

■

BYTE CONTROL: UB

/LB

■

PROGRAMMABLE PARTIAL ARRAY

■

TRI-STATE COMMON I/O

■

8 WORD PAGE ACCESS CAPABILITY: 25ns

■

PARTIAL POWER-DOWN MODES

– Deep Power-Down

– 4 Mbit Partial Power-Down

– 8 Mbit Partial Power-Down

– 16 Mbit Partial Power-Down

December 2004

1/17

M36W0R6050T0, M36W0R6050B0

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address Input (A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Chip Enable (E

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Output Enable (G

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Enable (W

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Write Protect (WP

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Reset (RP

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Latch Enable (L

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Clock (K

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Flash Wait (WAIT

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E1

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Chip Enable (E2

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSRAM Output Enable (G

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Write Enable (W

).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Upper Byte Enable (UB

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PSRAM Lower Byte Enable (LB

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDF

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CCP

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DDQ

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PPF

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

-O

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2/17

M36W0R6050T0, M36W0R6050B0

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.

Figure 5.

Figure 6.

Table 5.

Table 6.

Table 7.

Table 8.

Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 14

Table 9. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data 14

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

-O

3/17

M36W0R6050T0, M36W0R6050B0

SUMMARY DESCRIPTION

The M36W0R6050T0 and M36W0R6050B0 com-

bine two memory devices in a Multi-Chip Package:

a 64-Mbit, Multiple Bank Flash memory, the

M58WR064FT/B, and a 32-Mbit Pseudo SRAM,

the M69AR048B. Recommended operating condi-

tions do not allow more than one memory to be ac-

tive at the same time.

The memory is offered in a Stacked TFBGA88

(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-

age.

In addition to the standard version, the packages

are also available in Lead-free version, in compli-

ance with JEDEC Std J-STD-020B, the ST ECO-

PACK 7191395 Specification, and the RoHS

(Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free solder-

ing processes.

The memory is supplied with all the bits erased

(set to ‘1’).

Figure 2. Logic Diagram

DDQ

DDF

A0-A21

DQ0-DQ15

PPF

CCP

Table 1. Signal Names

A0-A20

DQ0-DQ15

DDF

DDQ

PPF

CCP

Common Address Inputs

Common Data Input/Output

Flash Memory Power Supply

Common Flash and PSRAM Power

Supply for I/O Buffers

Common Flash Optional Supply Voltage

for Fast Program & Erase

Ground

PSRAM Power Supply

Not Connected Internally

Do Not Use as Internally Connected

Flash Memory

A21

Address Input for the Flash memory only

Latch Enable input

Chip Enable input

Output Enable input

M36W0R6050T0

M36W0R6050B0

WAIT

-O

WAIT

Write Enable input

Reset input

Write Protect input

Burst Clock

Wait Data in Burst Mode

PSRAM

Chip Enable input

Output Enable input

Write Enable input

Power-down input

Upper Byte Enable input

Lower Byte Enable input

VSS

AI09378

4/17

M36W0R6050T0, M36W0R6050B0

Figure 3. TFBGA Connections (Top view through package)

A18

A19

VSS

VDDF

A21

A11

LBP

VSS

A12

A17

VPPF

A13

WPF

A20

A10

A15

UBP

RPF

DQ8

DQ2

DQ10

DQ5

DQ0

DQ1

DQ3

VSS

DQ9

-O

DQ12

DQ4

VDDP

DQ13

DQ14

DQ6

WAITF

DQ7

DQ15

A14

A16

DQ11

VDDQ

E2P

VDDQ

VDDF

VSS

AI08525

5/17

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Is it Rohs certified?	incompatible	conform to	conform to	incompatible	conform to	incompatible	conform to
Maker	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	8 X 10 MM, 0.80 MM PITCH, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, TFBGA-88	8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88
Contacts	88	88	88	88	88	88	88
Reach Compliance Code	not_compliant	compliant	unknown	not_compliant	unknow	_compli	unknow
Maximum access time	85 ns	85 ns	85 ns	85 ns	85 ns	85 ns	85 ns
Other features	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16	PSRAM IS ORGANIZED AS 2M X 16
JESD-30 code	R-PBGA-B88	R-PBGA-B88	R-PBGA-B88	R-PBGA-B88	R-PBGA-B88	R-PBGA-B88	R-PBGA-B88
JESD-609 code	e0	e1	e1	e0	e1	e0	e1
length	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm
memory density	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bi	67108864 bi	67108864 bi
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16	16	16	16	16	16
Mixed memory types	FLASH+PSRAM	FLASH+PSRAM	FLASH+PSRAM	FLASH+PSRAM	FLASH+PSRAM	FLASH+PSRAM	FLASH+PSRAM
Number of functions	1	1	1	1	1	1	1
Number of terminals	88	88	88	88	88	88	88
word count	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000	4000000	4000000	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C
organize	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA88,8X12,32	BGA88,8X12,32	BGA88,8X12,32	BGA88,8X12,32	BGA88,8X12,32	BGA88,8X12,32	BGA88,8X12,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	260	NOT SPECIFIED	260	NOT SPECIFIED	260
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum standby current	0.0001 A	0.0001 A	0.0001 A	0.0001 A	0.0001 A	0.0001 A	0.0001 A
Maximum slew rate	0.045 mA	0.045 mA	0.045 mA	0.045 mA	0.045 mA	0.045 mA	0.045 mA
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	TIN SILVER COPPER	TIN SILVER COPPER	Tin/Lead (Sn/Pb)	TIN SILVER COPPER	Tin/Lead (Sn/Pb)	TIN SILVER COPPER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm

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Light-controlled regulated power supply (output voltage drops when exposed to light)

Computer motherboard circuit diagram 810 2_33

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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