576Mb: x9 x18 x36 CIO RLDRAM 2
Features
CIO RLDRAM 2
MT49H64M9 – 64 Meg x 9 x 8 Banks
MT49H32M18 – 32 Meg x 18 x 8 Banks
MT49H16M36 – 16 Meg x 36 x 8 Banks
Features
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
– 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O
– 8 banks
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to op-
timize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (16K refresh for each bank; 128K re-
fresh command must be issued in total each 32ms)
• HSTL I/O (1.5V or 1.8V nominal)
•
–Ω
matched impedance outputs
• 2.5V V
EXT
, 1.8V V
DD
, 1.5V or 1.8V V
DDQ
I/O
• On-die termination (ODT) R
TT
Options
1
• Clock cycle timing
– 1.875ns @
t
RC = 15ns
– 2.5ns @
t
RC = 15ns
– 2.5ns @
t
RC = 20ns
– 3.3ns @
t
RC = 20ns
• Configuration
– 64 Meg x 9
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (T
C
= –40°C to +95°C;
T
A
= –40°C to +85°C)
• Package
– 144-ball μBGA
– 144-ball μBGA (Pb-free)
– 144-ball FBGA
– 144-ball FBGA (Pb-free)
• Revision
Note:
Marking
-18
-25E
-25
-33
64M9
32M18
16M36
None
IT
FM
BM
TR
SJ
:A/:B
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on
www.micron.com
for availa-
ble offerings.
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
BGA Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s web site at
micron.com.
Figure 1: Part Numbers
Example Part Number:
MT49H16M36SJ-25 :B
-
MT49H
Configuration I/O Package
Speed Temp.
:
Rev.
Configuration
64 Meg x 9
32 Meg x 18
16 Meg x 36
64M9
32M18
16M36
I/O
Common None
Separate
C
Revision
Rev. A
Rev. B
Temperature
:A
:B
Package
144-ball μBGA
144-ball μBGA (Pb-free)
144-ball FBGA
144-ball FBGA (Pb-free)
FM
BM
TR
SJ
Commercial
Industrial
Speed Grade
-18
-25E
-25
-33
t
CK
t
CK
t
CK
t
CK
None
IT
= 1.875ns
= 2.5ns
= 2.5ns
= 3.3ns
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
Contents
General Description ......................................................................................................................................... 7
Functional Block Diagrams ............................................................................................................................... 8
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ....................................................................................................................................... 16
Electrical Specifications – I
DD
.......................................................................................................................... 18
Absolute Maximum Ratings ............................................................................................................................ 22
AC and DC Operating Conditions .................................................................................................................... 23
Input Slew Rate Derating ................................................................................................................................ 26
Notes ............................................................................................................................................................. 31
Temperature and Thermal Impedance ............................................................................................................ 32
Commands .................................................................................................................................................... 34
MODE REGISTER SET (MRS) ...................................................................................................................... 35
Configuration Tables .............................................................................................................................. 37
Burst Length (BL) ................................................................................................................................... 37
Address Multiplexing .............................................................................................................................. 39
DLL RESET ............................................................................................................................................. 39
Drive Impedance Matching .................................................................................................................... 39
On-Die Termination (ODT) ..................................................................................................................... 40
WRITE ....................................................................................................................................................... 41
READ ......................................................................................................................................................... 42
AUTO REFRESH (AREF) .............................................................................................................................. 43
INITIALIZATION ............................................................................................................................................ 43
WRITE ........................................................................................................................................................... 47
READ ............................................................................................................................................................. 52
AUTO REFRESH ............................................................................................................................................. 60
On-Die Termination ....................................................................................................................................... 61
Multiplexed Address Mode .............................................................................................................................. 64
Address Mapping in Multiplexed Address Mode ........................................................................................... 67
Configuration Tables in Multiplexed Address Mode ...................................................................................... 67
REFRESH Command in Multiplexed Address Mode ..................................................................................... 68
IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 72
Disabling the JTAG Feature ......................................................................................................................... 72
Test Access Port (TAP) ..................................................................................................................................... 72
Test Clock (TCK) ......................................................................................................................................... 72
Test Mode Select (TMS) .............................................................................................................................. 72
Test Data-In (TDI) ...................................................................................................................................... 73
Test Data-Out (TDO) .................................................................................................................................. 73
TAP Controller ................................................................................................................................................ 73
Test-Logic-Reset ......................................................................................................................................... 73
Run-Test/Idle ............................................................................................................................................. 73
Select-DR-Scan .......................................................................................................................................... 73
Capture-DR ................................................................................................................................................ 73
Shift-DR ..................................................................................................................................................... 73
Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 74
Update-DR ................................................................................................................................................. 74
Instruction Register States .......................................................................................................................... 74
Performing a TAP RESET ................................................................................................................................. 75
TAP Registers ................................................................................................................................................. 75
Instruction Register .................................................................................................................................... 75
Bypass Register .......................................................................................................................................... 75
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
Boundary Scan Register ..............................................................................................................................
Identification (ID) Register ..........................................................................................................................
TAP Instruction Set .........................................................................................................................................
EXTEST ......................................................................................................................................................
IDCODE .....................................................................................................................................................
High-Z .......................................................................................................................................................
CLAMP ......................................................................................................................................................
SAMPLE/PRELOAD ....................................................................................................................................
BYPASS ......................................................................................................................................................
Reserved for Future Use ..............................................................................................................................
76
76
76
77
77
77
77
77
78
78
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
List of Figures
Figure 1: Part Numbers .................................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 7
Figure 3: 64 Meg x 9 Functional Block Diagram ................................................................................................. 8
Figure 4: 32 Meg x 18 Functional Block Diagram ............................................................................................... 9
Figure 5: 16 Meg x 36 Functional Block Diagram ............................................................................................. 10
Figure 6: 144-Ball μBGA ................................................................................................................................. 16
Figure 7: 144-Ball FBGA ................................................................................................................................. 17
Figure 8: Clock Input ..................................................................................................................................... 25
Figure 9: Nominal
t
AS/
t
CS/
t
DS and
t
AH/
t
CH/
t
DH Slew Rate ........................................................................... 29
Figure 10: Example Temperature Test Point Location ...................................................................................... 33
Figure 11: MODE REGISTER Command ......................................................................................................... 35
Figure 12: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 36
Figure 13: Read Burst Lengths ........................................................................................................................ 38
Figure 14: On-Die Termination-Equivalent Circuit .......................................................................................... 40
Figure 15: WRITE Command ......................................................................................................................... 41
Figure 16: READ Command ........................................................................................................................... 42
Figure 17: AUTO REFRESH Command ........................................................................................................... 43
Figure 18: Power-Up/Initialization Sequence ................................................................................................. 45
Figure 19: Power-Up/Initialization Flow Chart ................................................................................................ 46
Figure 20: WRITE Burst ................................................................................................................................. 47
Figure 21: Consecutive WRITE-to-WRITE ....................................................................................................... 48
Figure 22: WRITE-to-READ ............................................................................................................................ 49
Figure 23: WRITE-to-READ (Separated by Two NOPs) ..................................................................................... 50
Figure 24: WRITE – DM Operation ................................................................................................................. 51
Figure 25: Basic READ Burst Timing ............................................................................................................... 52
Figure 26: Consecutive READ Bursts (BL = 2) .................................................................................................. 53
Figure 27: Consecutive READ Bursts (BL = 4) .................................................................................................. 53
Figure 28: READ-to-WRITE ............................................................................................................................ 54
Figure 29: Read Data Valid Window for x9 Device ........................................................................................... 55
Figure 30: Read Data Valid Window for x18 Device .......................................................................................... 56
Figure 31: Read Data Valid Window for x36 Device .......................................................................................... 58
Figure 32: AUTO REFRESH Cycle ................................................................................................................... 60
Figure 33: READ Burst with ODT .................................................................................................................... 61
Figure 34: READ-NOP-READ with ODT .......................................................................................................... 62
Figure 35: READ-to-WRITE with ODT ............................................................................................................ 63
Figure 36: Command Description in Multiplexed Address Mode ..................................................................... 64
Figure 37: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 65
Figure 38: Mode Register Definition in Multiplexed Address Mode .................................................................. 66
Figure 39: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 68
Figure 40: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 68
Figure 41: WRITE-to-READ with Multiplexed Addressing ................................................................................ 69
Figure 42: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 70
Figure 43: READ-to-WRITE with Multiplexed Addressing ................................................................................ 70
Figure 44: TAP Controller State Diagram ......................................................................................................... 74
Figure 45: TAP Controller Block Diagram ........................................................................................................ 75
Figure 46: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 78
Figure 47: TAP Timing ................................................................................................................................... 79
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
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