EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

ABM4B-FREQ1-CL-R100-B-Y-2-T

Description
Parallel - Fundamental Quartz Crystal, 6MHz Min, 6.999MHz Max, ROHS COMPLIANT PACKAGE-4
CategoryPassive components    Crystal/resonator   
File Size229KB,3 Pages
ManufacturerAbracon
Websitehttp://www.abracon.com/index.htm
Environmental Compliance
Download Datasheet Parametric View All

ABM4B-FREQ1-CL-R100-B-Y-2-T Overview

Parallel - Fundamental Quartz Crystal, 6MHz Min, 6.999MHz Max, ROHS COMPLIANT PACKAGE-4

ABM4B-FREQ1-CL-R100-B-Y-2-T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerAbracon
package instructionROHS COMPLIANT PACKAGE-4
Reach Compliance Codecompliant
Other featuresTAPE AND REEL
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.003%
frequency tolerance20 ppm
Manufacturer's serial numberABM4B
Installation featuresSURFACE MOUNT
Maximum operating frequency6.999 MHz
Minimum operating frequency6 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
physical sizeL7.0XB5.0XH1.4 (mm)/L0.276XB0.197XH0.055 (inch)
Series resistance100 Ω
surface mountYES
China's chips look forward to new breakthroughs
China's chips face embarrassment, looking forward to new breakthroughs 2006-6-22  Once upon a time, Chinese IC design companies seemed to have achieved a "clustered breakthrough in 'Chinese chips'". H...
ehk PCB Design
Hiring embedded software engineer
Headhunter position [Beijing] Job responsibilities: 1. Responsible for the company's video security project development. 2. Responsible for network video protocol (RTSP, RTP, SIP) analysis, video data...
ff318421749 Recruitment
dsp28335 AD sampling DMA transfer
[size=4]Three modes are configured: single mode, continuous mode and DMA transfer[/size] [size=4]The single mode is to call the acquisition function once, collect at a specified AD port, and sample wh...
fish001 DSP and ARM Processors
EEWORLD University ---- Webinar - How to quickly design power rails for Xilinx FPGA and SoC
Webinar - How to quickly design power rails for Xilinx FPGAs and SoCs : https://training.eeworld.com.cn/course/5283In this webinar in cooperation with farnell it will be discussed how to use the Texas...
hi5 Talking
EEWORLD University----simulink video tutorial
Simulink video tutorial : https://training.eeworld.com.cn/course/26681Simulink video tutorial...
桂花蒸 Embedded System
Interleaved CCM Totem Pole Bridgeless Power Factor Correction (PFC) Reference Design
This design illustrates how to control this power stage using a C2000 MCU and LMG3410 GaN FET modules.To improve efficiency, this design uses adaptive dead time and phase shedding methods. Nonlinear v...
Jacktang Microcontroller MCU

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号