THIS SPEC IS OBSOLETE
Spec No:
002-01235
Spec Title:
S29AL004D, 4-MBIT (512K X 8-BIT/256K X 16-
BIT), 3 V BOOT SECTOR FLASH
Replaced by:
NONE
S29AL004D
4-Mbit (512K x 8-Bit/256K x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– 2.7 to 3.6 volt read and write operations for battery-powered
applications
Manufactured on 200 nm Process Technology
– Compatible with 0.32 µm Am29LV400B and MBM29LV400T/BC
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword
sectors (word mode)
– Supports full chip erase
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and
erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies
data at specified addresses
Compatibility with JEDEC Standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Sector Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Performance Characteristics
High Performance
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
Ultra-low Power Consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode current
– 9 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SO
Software Features
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
Cypress Semiconductor Corporation
Document Number: 002-01235 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 25, 2017
S29AL004D
General Description
The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-
ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device requires only a single, 3.0 volt V
CC
supply to perform read, program, and erase operations. A
standard EPROM programmer can also be used to program and erase the device.
This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the
Am29LV400B and MBM29LV400T/BC, which were manufactured using 320 nm process technology.
The standard device offers access times of 70 and 90 ns, allowing high speed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the
Embedded Program
algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle is completed, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector protection
feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend
feature enables the user to put erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-01235 Rev. *B
Page 2 of 46
S29AL004D
Contents
1.
2.
3.
3.1
4.
5.
6.
7.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
10.1
11.1
11.2
11.3
12.
12.1
12.2
12.3
12.4
12.5
12.6
12.7
14.
14.1
14.2
14.3
14.4
14.5
14.6
14.7
16.
17.
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
Connection Diagrams..................................................
5
Special Handling Instructions for FBGA Package.......... 6
Pin Configuration.........................................................
6
Logic Symbol
............................................................... 7
Ordering Information (Standard Products)................
7
Device Bus Operations................................................
9
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................. 10
Program and Erase Operation Status.......................... 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 10
RESET#: Hardware Reset Pin..................................... 11
Output Disable Mode ................................................... 11
Autoselect Mode .......................................................... 12
Sector Protection/Unprotection .................................... 12
Temporary Sector Unprotect........................................ 13
Hardware Data Protection............................................ 15
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Word/Byte Program Command Sequence...................
Chip Erase Command Sequence ................................
Sector Erase Command Sequence .............................
Erase Suspend/Erase Resume Commands ................
Write Operation Status
..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
DQ3: Sector Erase Timer.............................................
15
15
15
16
16
17
18
18
20
20
21
22
22
22
23
23
30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15
x 6.15 mm .....................................................................40
30.3 SO 044—44-Pin Small Outline Package ...................... 41
31.
31.1
31.2
31.3
31.4
31.5
31.6
31.7
Revision Summary......................................................
42
Revision A0 (November 12, 2004)................................ 42
Revision A1 (February 18, 2005) .................................. 42
Revision A2 (June 1, 2005)........................................... 42
Revision A3 (June 21, 2005)......................................... 43
Revision A4 (May 22, 2006).......................................... 43
Revision A5 (June 22, 2006)......................................... 43
Revision A6 (February 27, 2009) .................................. 43
Absolute Maximum Ratings......................................
24
Operating Ranges
...................................................... 25
18. DC Characteristics.....................................................
25
18.1 Zero Power Flash......................................................... 26
19.
21.
Test Conditions
.......................................................... 27
Key to Switching Waveforms....................................
28
22. AC Characteristics.....................................................
29
22.1 Read Operations.......................................................... 29
25.1 Erase/Program Operations .......................................... 32
28.
Erase And Programming Performance....................
37
30. Physical Dimensions
................................................. 39
30.1 TS 048—48-Pin Standard TSOP ................................. 39
Document Number: 002-01235 Rev. *B
Page 3 of 46
S29AL004D
1.
Product Selector Guide
Family Part Number
Speed Options
Full Voltage Range: V
CC
= 2.7–3.6 V
55
55
55
25
S29AL004D
70
70
70
30
90
90
90
35
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note
See
AC Characteristics on page 29
for full specifications.
2. Block Diagram
RY/BY#
V
CC
V
SS
Sector Switches
DQ0–DQ15 (A-1)
RESET#
Erase Voltage
Generator
Input/Output
Buffers
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
Y-Decoder
Y-Gating
Timer
Address Latch
V
CC
Detector
X-Decoder
Cell Matrix
A0–A17
Document Number: 002-01235 Rev. *B
Page 4 of 46
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