EM MICROELECTRONIC-MARIN SA
H6060
Self Recovering Watchdog
Features
Self recovering watchdog function: reset goes active
after the 1st timeout period, reset goes inactive
again after the 2nd timeout period, repeated active
reset signal until the system recovers
Standard timeout period and power-on reset time
(100 ms), externally programmable if required
Unregulated DC monitoring (V
IN
) with 3 standard or
programmable trigger voltages for: power-on reset
initialization, advanced power-fail warning (SAVE),
reset at power-down (RES)
Regulated DC monitoring (V
DD
): power-on reset
initialization enabled only if V
DD
≥
3.5 V
Internal voltage reference
Works down to 1.6 V supply voltage
Push-pull or Open drain outputs
Low current consumption
Available for normal and extended temperature
ranges
DIP8 and SO8 package
Typical Operating Configuration
Voltage
Regulator
5V
V
IN
TCL
V
SS
H6060
V
DD
RES
SAVE
RES
NMI
Micro-
processor
RES
I/O
GND
Description
The H6060 is a monolithic low-power CMOS device
combining a programmable timer and a series of voltage
comparators on the same chip. The device is specially
suited for watchdog functions such as microprocessor
and supply voltage monitoring. If the
µP
system
malfunctions, the watchdog will recover it by issuing
repeated active reset signals. The voltage monitoring
part provides double security by combining both the
unregulated voltage (V
IN
) and the regulated voltage (V
DD
)
monitoring simultaneously. The H6060 initializes the
power-on reset after V
IN
reaches V
SH
(see table 4) and
V
DD
rises above 3.V. If V
IN
drops below V
SL
(see table 4),
the H6060 gives an advanced warning signal for
register saving and if the voltage drops further below V
RL
(see table 4), RES and RES go active. The H6060
functions at any supply voltage down to 1.6 V and is
therefore particularly suited for start-up and shut-down
control of microprocessor systems.
Fig. 1
Pin Assignment
DIP8 / SO8
V
IN
TCL
RC
V
SS
H6060
V
DD
RES
SAVE
RES
Applications
Microprocessor and microcontroller systems
Point of sales equipment
Telecom products
Automotive subsystems
Fig. 2
1
H6060
Absolute Maximum Ratings
Parameter
Voltage V
DD
to V
SS
Voltage at any pin to V
SS
Voltage at any pin to V
DD
(except V
IN
)
Voltage at V
IN
to V
SS
Current at any output
Storage temperature
Symbol
V
DD
V
MIN
V
MAX
V
INMAX
I
MAX
T
STO
Conditions
−
0.3 to + 8 V
−
0.3
+ 0.3
+
15 V
±
10 mA
−65...+150 °C
Table 1
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified operating conditions may affect device
reliability or cause malfunction.
precautions must be taken as for any other CMOS
component. Unless otherwise specified, proper
operation can only occur when all terminal voltages are
kept within the supply voltage range. Unused inputs
must always be tied to a defined logic voltage level.
Operating Conditions
Parameter
Symbol Min. Typ Max. Units
-40
1.6
0
0
+85
5.5
V
DD
12
1
°C
V
V
V
µF
k
Ω
Table 2
Operating temperature
T
AI
Industrial
Supply voltage
V
DD
Comparator input voltage
Version 13, 14, 15, 16 V
IN
Version 11,12
V
IN
RC-oscillator programm-
ing (see Fig. 15)
∗
External capacitance C1
R1
External resistance
∗
Handling Procedures
This device has built-in protection against high static
voltages or electric fields;
however, anti-static
10
Leakage
<
1
µA
Electrical Characteristics
Parameter
V
DD
activation threshold
V
DD
deactivation threshold
Supply current
Input V
IN
,
TCL
Leakage current
Input current on pin V
IN
TCL input low level
TCL input high level
SAVE , RES , RES outputs
Leakage currents
Drive currents (all versions)
Drive currents
(versions 12, 14,16)
1)
1)
V
DD
= 5.0 V, T
A
=
−40
to +85
°C,
unless otherwise specified
Symbol
V
ON
V
OFF
I
DD
I
IP
I
IN
V
IL
V
IH
I
OLK
I
OL
I
OL
I
OL
I
OH
I
OH
I
OH
Test Conditions
T
A
= 25
°C
T
A
= 25
°C
RC open, TCL at V
DD
or V
SS
V
SS
≤
V
IP
≤
V
DD
;
T
A
= 85
°C
Versions 11, 12; V
IN
= 10 V
Min.
3
Typ.
V
ON
−
0.3
80
0.005
100
Max.
3.5
140
1
180
0.8
Units
V
V
µ
A
µ
A
µ
A
2.4
Versions 11, 13, 15;
V
OUT
= V
DD
V
OL
= 0.4 V
V
DD
= 3.5 V; V
OL
= 0.4 V
V
DD
= 1.6 V; V
OL
= 0.4 V
V
OH
= 4.0 V
V
DD
= 3.5 V; V
OH
= 2.8 V
V
DD
= 1.6 V; V
OH
= 1.2 V
0.05
8
8
V
V
1
µ
A
3.2
2
80
3.2
2
80
mA
mA
µ
A
mA
mA
µ
A
Table 3
Versions: 11, 13, 15 = open drain outputs; 12, 14, 16 = push-pull outputs
Voltage thresholds at T
A
= 25
°C
V
IN
Surveillance
Version
1)
11, 12
13, 14
15, 16
Comparator
Reference
V
DD
V
DD
Band-gap reference
Input Resistance
on V
IN
(R
VIN
)
100kΩ
∼100MΩ
∼100MΩ
V
SH
9.00
2.25
2.00
Threshold
V
SL
V
RL
8.00
2.00
1.95
7.00
2)
1.75
2)
1.90
Thresholds
Tolerance
Ratio
Tolerance
3)
±5%
±5%
±10%
±2%
±2%
±2%
Table 4
1)
2)
Versions: 11, 13, 15 = open drain ouputs; 12, 14, 16 = push-pull outputs
at V
DD
= 5 V
3)
Threshold ratio tolerance is defined as the tolerance of V
SH
/ V
SL
and V
SL
/ V
RL
.
2
H6060
Timing Characteristics
V
DD
= 5.0 V, T
A
=
−40 °C
to
+85 °C,
unless otherwise specified
Parameter
Propagation delays
TCL to output pins
V
IN
to output pins
Logic transition times on
all output pins
Timeout period
T
TCL
input pulse width
Power-on reset debounce
V
IN
low pulse
Symbol
T
DIDO
T
AIDO
T
TR
T
TO
T
TO
T
TCL
T
DB
T
VINL
Test Conditions
Min.
Typ.
250
4
30
Max.
500
10
100
160
200
Units
ns
µs
ns
ms
ms
ns
ms
µs
Table 5
Excluding debounce time T
DB
Load 10 kΩ, 100 pF
RC open, unshielded, T
A
= 25
°C
RC open, unshielded (not tested)
60
45
150
100
T
TO
/64
Where debounce time T
DB
Is guaranteed
10
Timing Waveforms
Voltage Reaction: V
DD
Monitoring
V
DD
V
ON
V
OFF
V
IN
monitoring enabled
Fig. 3
Voltage Reaction: V
IN
Monitoring
V
IN
V
SH
V
SL
V
RL
T
VINL
Conditions:
V
DD
>
V
ON
.
No timeout.
T
TO
0
SAVE
RES
RES
Timer
Start
Power-on Reset
T
TO
T
DB
T
DB
Timer
Stop Timer
Start
Power-on Reset
No Power-on Reset
(as V
IN
>
V
RL
)
Fig. 4
3
H6060
Timer Reaction
T
TCL
Conditions:
V
IN
>
V
RL
after
power-up sequence
T
TO
T
TO
T
TO
TCL
RES
T
TO
RES
Timer
Reset
Timeout
Timer
Reset
Timer
Reset
Fig. 5
Combined Voltage and Timer Reaction
V
IN
V
SH
V
SL
V
RL
T
DB
SAVE
RES
RES
TCL
Initialisation
T
TO
T
TO
T
TO
RES
RES
Timeout Recover
Timer
Reset
Timer
Stop
Fig. 6
Block Diagram
V
DD
1
2
V
IN
Band-Gap
Reference
V
SH
+
+
Save
Control
SAVE
V
SL
+
V
RL
Reset
Control
RES
RES
+
3
V
SS
RC
Version Connections
11, 12
1 and 3
13, 14
1
15, 16
2
OSC
Timer
TCL
4
Fig. 7
H6060
Pin Description
Pin Name
1
2
3
4
5
6
7
8
V
IN
TCL
RC
V
SS
RES
SAVE
RES
V
DD
Function
Voltage sense input
Timer clear input signal
RC oscillator tuning input
GND terminal
Active low reset output
Save output
Active high reset output
Positive supply voltage terminal
Table 6
Version 11, 12:
have an internal voltage divider for
direct monitoring of the unregulated voltage without
external components.
Voltage
Regulator
5V
V
DD
RES
SAVE
RES
V
SS
Functional Description
Supply Lines
The circuit is powered through the V
DD
and V
SS
pins. It
monitors both its own V
DD
supply and a voltage applied
to the V
IN
input.
V
DD
Monitoring
During power-up the V
IN
monitoring is disabled and RES
,
RES and SAVE stay active low as long as V
DD
is below
V
ON
(3.5 V). As soon as V
DD
reaches the V
ON
level, the
state of the outputs depend on the watchdog timer and
the voltage at V
IN
relative to the thresholds (see Fig. 4). If
the supply voltage V
DD
falls back below V
OFF
(V
ON
– 0.3 V)
the watchdog timer and the V
IN
monitoring are disabled
and the outputs RES, RES and SAVE become active.
The V
DD
line should be free of voltage spikes.
V
IN
Monitoring
The analog voltage comparators compare the voltage
applied to V
IN
(typically connected to the input of the
voltage regulator) with the stabilized supply voltage V
DD
(versions 11, 12, 13, 14) or with the bandgap voltage
(versions 15, 16) (see Fig. 7). At power-up, when V
DD
reached V
ON
and V
IN
reaches the V
SH
level, the SAVE
output goes inactive, and the timer starts running,
setting RES and RES in active after the time T
TO
(see.
Fig. 4). If V
IN
falls below V
SL
, the SAVE output goes
active and stays active until V
IN
rises again above V
SH
. If
V
IN
falls below the voltage V
RL
, RES and RES will
become active and the on-chip timer will stop. When V
IN
rises again above V
SH
, the timer will initiate a power-up
sequence. The RES and RES outputs may however be
influenced independently of the voltage V
IN
by the timer
action, see section
″Combined
Voltage and Timer
Action”. Monitoring the rough DC side of the regulator,
as shown in Fig. 12, is the only way to have advanced
warning of power-down. Spikes on V
IN
should be filtered
if they are likely to exceed the value (V
SL
– V
RL
).
The combination of V
IN
and V
DD
monitoring provide high
system security: if V
IN
rises much faster than V
DD
, then
the device starts the power-on sequence only when V
DD
reached V
ON
(Fig. 11). Short circuits on the regulated
supply voltage can be detected.
Voltage Thresholds on V
IN
The
H6060
is available with 3 different sets of
thresholds:
Note:
internal threshold levels: 9/8/7 V at V
DD
= 5 V
(thresholds relative to V
DD
, see table 4 and
Fig. 8
fig. 4) R
VIN
= ~100 kΩ
Version 13, 14:
monitor the unregulated voltage and are
ideal for programming of the V
IN
voltage thresholds.
Fixed resistor values can be used for programming.
any voltage
Voltage
Regulator
V
IN
5V
H6060 11, 12
H6060 13, 14
V
IN
V
DD
RES
SAVE
RES
V
SS
Note:
internal threshold levels: 2.25/2.00/1.75 V
at V
DD
= 5 V (thresholds relative to V
DD
, see
Fig. 9
table 4 and fig. 4) R
VIN
= ~100 MΩ
Version 15, 16:
monitor the regulated voltage. They are
suited to applications where the unregulated voltage is
not available. (The tolerance is
±
10%, see table 4. For
tighter tolerances, trimming can be used, see fig. 10).
H6060 15, 16
V
IN
V
DD
RES
SAVE
RES
V
SS
Note:
internal threshold levels: 2.00/1.95/1.90 V
(thresholds relative to internal bandgap
reference) R
VIN
= ~100 MΩ
Fig. 10
5