— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.8V compatible I/O signals (1.65-1.95 V)
— 1.5V compatible I/O signals (1.35-1.70 V)
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/
16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
SecSi™ (Secured Silicon) Sector region
— 128 words accessible through a command sequence,
64words for the Factory SecSi™ Sector and 64words
for the Customer SecSi™ Sector.
Sector Architecture
4 Kword x 16 boot sectors, eight at the top of the address
range, and eight at the bottom of the address range
—
WS128J:
4 Kword X 16, 32 Kword x 254 sectors
Bank A : 4 Kword x 8, 32 Kword x 31 sectors
Bank B : 32 Kword x 96 sectors
Bank C : 32 Kword x 96 sectors
Bank D : 4 Kword x 8, 32 Kword x 31 sectors
—
WS064J:
4 Kword x 16, 32 Kword x 126 sectors.
Bank A : 4 Kword x 8, 32 Kword x 15 sectors
Bank B : 32 Kword x 48 sectors
Bank C : 32 Kword x 48 sectors
Bank D : 4 Kword x 8, 32 Kword x 15 sectors
WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,
WS064J : 80-ball (7 mm x 9 mm) FBGA package
Cyclling Endurance : 1,000,000 cycles per sector
typical
Data retention : 20-years typical
ADVANCE
INFORMATION
Performance Charcteristics
Read access times at 104/80/66 MHz
— Burst access times of 7.0/9.1/11.2 ns @ 30 pF at
industrial temperature range
— Synchronous latency of 45.5/46/56 ns (at 30 pF)
— Asynchronous random access times of 45/45/55 ns
(at 30 pF)
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA @ 80Mhz
— Simultaneous Operation: 25 mA @ 80Mhz
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Hardware Features
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
WP# input
— Write protect (WP#) function allows protection of
four outermost boot sectors, regardless of sector
protect status
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
Publication Number
WS128J/064J_00
Revision
A
Amendment
1
Issue Date
October 6, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
A D V A N C E
Software Features
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29BDS, Am29BDD,
Am29BL, and MBM29BS families
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
I N F O R M A T I O N
2
S29WS128J/064J
WS128J/064J_00_A1_E
October 6, 2004
A D V A N C E
I N F O R M A T I O N
General Description
The S29WS128J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write,
Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits
each. This device uses a single V
CC
of 1.65 to 1.95 V to read, program, and erase the
memory array. A 12.0-volt V
HH
on ACC may be used for faster program performance if
desired. The device can also be programmed in standard EPROM programmers.
At 104 MHz, the device provides a burst access of 7.0 ns at 30 pF with a latency of 45.5
ns at 30 pF. At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a la-
tency of 46 ns at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF
with a latency of 56 ns at 30 pF. The device operates within the industrial temperature
range of -40°C to +85°C and the wireless temperature range of -25°C to +85°C. The de-
vice is offered in Various FBGA packages.
The Simultaneous Read/Write architecture provides
simultaneous operation
by divid-
ing the memory space into four banks. The device can improve overall system perfor-
mance by allowing a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
Quantity
Bank
A
B
C
D
128Mb
8
31
96
96
31
8
64 Mb
8
15
48
48
15
8
Size
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
The VersatileIO™ (V
IO
) control allows the host system to set the voltage levels that the
device generates at its data outputs and the voltages tolerated at its data inputs to the
same voltage level that is asserted on the V
IO
pin.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-
put Enable (OE#) to control asynchronous read and write operations. For burst opera-
t i on s , t h e d e v i c e a dd i t i o n a l l y r e q u i r e s Re a d y ( R D Y ) , a n d C l o c k ( C L K ) . T h i s
implementation allows easy interface with minimal glue logic to a wide range of micropro-
cessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to the de-
vice. The user can preset the burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock edges, either
rising or falling. The active clock edge initiates burst accesses and determines when data
will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-
supply Flash standard.
Commands are written to the command register using standard
microprocessor write timing. Register contents serve as inputs to an internal state-ma-
chine that controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the user to put erase or program
on hold for any period of time to read data from, or program data to, any sector that is
not selected for erasure. True background erase can thus be achieved. If a read is needed
from the SecSi™ Sector area (One Time Program area) after an erase suspend, then the
user must use the proper command sequence to enter and exit this region. Program sus-
pend is also offered.
The
hardware RESET# pin
terminates any operation in progress and resets the internal
state machine to reading array data. The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the device, enabling the system microproces-
sor to read boot-up firmware from the Flash memory device.
October 6, 2004
WS128J/064J_00_A1_E
S29WS128J/064J
3
A D V A N C E
I N F O R M A T I O N
The host system can detect whether a program or erase operation is complete by using
the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or
erase cycle has been completed, the device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically in-
hibits write operations during power transitions. The device also offers two types of data
protection at the sector level. When at V
IL
,
WP#
locks the four outermost boot sectors.
The device offers two power-saving features. When addresses have been stable for a
specified amount of time, the device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power consumption is greatly reduced in
both modes.
Spansion™ Flash memory products combine years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness. The de-
vice electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunnelling. The data is programmed using hot electron injection.
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