DimmDrive Solid State IDE Flash Module with Power Failure
Protection*
IDE36
DimmDrive Solid State IDE Flash Module
IDE33
FEATURES
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144 pin SO-DIMMpackage with IDE pinouts
Plug-and-play solid state disk
NAND Flash memory technology by SanDisk
3.3 V and 5.0 V power supply operation
16MB – 2GB memory density
Low power consumption
ECC error correction
512 Byte Sector compatible to IDE HD Drives
Supports true IDE mode
Commercial temperature range 0°C - +70°C
PFP Power Failure Protection Circuit (IDE36)
GENERAL DESCRIPTION
The DimmDrive WED7GxxxIDE36 is a high performance
single chip flash disk IDE module with Power Failure
Protection Circuit available in 144 Pin SO-DIMM
package.
The DimmDrive WED7GxxxIDE33 does not have the
additional PFP circuit.
The additional circuit provides protection against accidental
power loss. This circuit provides an internal power supply
and control logic to stop receiving data and complete
writing the last sector of data received. This is not intended
to be backup for the host system. It will only allow the
last sector received to finish writing and no more. It will
improve card integrity in applications with a high risk of
power failure. The read/write unit is 1 sector (512 bytes)
sequential access.
The module is based on SanDisk NAND Flash technology
and utilizes 128Mb, 256Mb, 512Mb or 1Gb memory
components to provide the maximum in module density.
The DimmDrive WED7GxxxIDE36/33 utilizes a SanDisk
Flash ChipSet controller for the SanDisk memory devices.
This interface allows a host computer to issue commands
to read or write blocks of memory in the Flash memory
array. The intelligence to manage the interface protocols,
data storage and retrieval as well as ECC, defect handling
and diagnostics are controlled by this device. Automatic
power management and clock control is handled by the
controller as well.
The DimmDrive WED7GxxxIDE36/33 module will have
the same functionality and capabilities of an intelligent ATA
(IDE) disk drive. Once the device has been configured
by the user, it appears to the host as a standard ATA disk
drive.
The on-board controller is a highly integrated solution
designed to handle all intelligent operations, even the rare
cases when new defects arise and need to be mapped
out or replaced by a spare. The hardware performs the
complicated task of ECC detection and correction and will
return good data to the host. The controller manages all
defects and errors and makes the Flash memory appear
POWER BACKUP FEATURES (IDE36)
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Added PFP circuit built in to preserve card integrity
during accidental power loss
PFP circuit may not prevent file/data loss if power
failure occurs during a long write operation
PFP control circuit prevents false operations after
power loss
Improves card integrity in applications with a high
risk of power failure
Minimum power backup time of 10ms
APPLICATIONS
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Embedded systems
Internet Access Devices
Set Top Boxes
WEB Browser
Routers, Networking
WEB phones, car PC, DVD, HPC
Medical and Telcom
Other applications requiring embedded or solid
state storage
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Point-of-sale
* Patent pending
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
as perfect memory to the host.
The DimmDrive WED7GxxxIDE36/33 module also
provides a more cost effective solution to the traditional
hard disk media. The module is perfect for applications
requiring upgrade ability to higher densities and for those
applications with limited space availability and power
consumption requirements.
Unlike standard IDE drives, no cables or extra space is
WED7GxxxIDE36
WED7GxxxIDE33
PRELIMINARY*
required. The module has no moving parts providing
significant reduction in power consumption and increasing
reliability. Simply insert the module into a standard 144
Pin SO-DIMM socket with IDE pinout and you then have
a bootable flash disk.
The DimmDrive WED7GxxxIDE36/33 is available with
memory densities of 16MB to 2GB.
MODULE PINOUT
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Notes:
Odd pins are NC (NO CONNECT).
“/” indicates signals active low.
* low for MASTER, high (open) for SLAVE
** pulled up
On the NC pins of the module, additional signals not used in the IDE mode may be
present.
SIGNAL
GND
V
CC
GND
NC
D7
NC
D8
NC
D6
NC
D9
NC
D5
NC
D10
NC
D4
NC
PIN
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
SIGNAL
D11
NC
D3
NC
D12
NC
D2
NC
D13
NC
D1
NC
D14
NC
D0
NC
D15
NC
PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
SIGNAL
CS0#
NC
NC
CS1#
IORD#
IOWR#
NC
NC
NC
NC
NC
IRQ
CSEL#*
RESET
IORDY**
NC
NC
NC
PIN
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
SIGNAL
A2
NC
NC
DASP#
PDIAG#
A1
A0
IOCS16#
V
CC
GND
NC
NC
NC
NC
NC
NC
NC
NC
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
SIGNAL DESCRIPTION
SIGNAL NAME
RESET
D(15-0)
DIR
I
I/O
PIN
100
70,62,54,46,38,30,
22,14,10,18,26,34,
42,50,58,66
84
WED7GxxxIDE36
WED7GxxxIDE33
PRELIMINARY*
IOWR
I
IORD
I
82
CSEL
I
98
IRQ
IOCS16
PDIAG
A(2-0)
CS0
CS1
DASP
O
O
I/O
I
I
I
I/O
96
124
118
110,120,122
74
80
116
IORDY
GND
Vcc
O
102
2,6,128
4,126
DESCRIPTION
HOST RESET. Reset signal from the host that is active on power up.
HOST DATA. These 16 lines carry the data between the controller and the host. The
low 8 lines transfer commands, status and ECC information between the host and the
controller.
I/O WRITE. This strobe pulse is used to clock data or commands on the host data
bus into the controller. The clocking will occur on the negative to positive edge of the
signal (trailing edge).
I/O READ. This is a read strobe generated by the host. This signal gates data or
status on the host bus and strobes the data from the controller into the host on the
low to high transition (trailing edge).
This internally pulled up signal is used to configure this device as a Master or a
Slave. When this pin is grounded by the host, this device is configured as a Master.
When this pin is high (or open), this device is configured as a Slave.
INTERRUPT REQUEST. This is an interrupt request from the controller to the host,
asking for service. The output of this signal is tri-stated when the interrupts are
disabled by the host.
I/O SELECT 16. This open drain output is asserted low by the controller to indicate to
the host the current cycle is a16 bit word data transfer.
PASS DIAGNOSTIC. This bi-directional open drain signal is asserted by the slave
after anExecute Diagnostic command to indicate to the master it has passed its
diagnostics.
HOST ADDRESS. These address lines are used to select the registers within the
controller task
fi
le.
HOST CHIP SELECT 0. This is a chip select signal that is used to select the
controller task
fi
le.
HOST CHIP SELECT 1. This is a chip select signal that is used to select the control
and diagnostic register.
DISK ACTIVE/SLAVE PRESENT. This open drain output signal is asserted low any
time the drive is active. In a master/slave configuration, this signal is used by the
slave to inform the master a slave is present.
This is an optional signal that is negated when the drive is not ready to respond to a
data transfer request. For the module this signal is not used, the pin is pulled up. As
long as the host obeys PIO mode 0 or 4 timing, the module is guaranteed to respond
properly.
GROUND.
POWER (3.3V – 5V)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIG. 1 BLOCK DIAGRAM
WED7GxxxIDE36
WED7GxxxIDE33
PRELIMINARY*
V
CC
Power Failure
Protection
Circuit (IDE36)
Internal V
CC
16
Internal V
CC
2
Control
Control
D15 – D8
SanDisk
Controller
AND
Flash
n
Data
D7 – D0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
POWER BACKUP TIMING
Shown in the following two figures are the differences in
operation between the WED7GxxxIDE33 module, and the
WED7GxxxIDE36 module with Power Failure Protection
Circuit.
Figure 1 shows how a sector is written to a NAND Flash.
The entire sector is received and then is written at one
time. The RDY/BSY line stays busy until proper writing
of the data is ensured. If power loss occurs before the
WED7GxxxIDE36
WED7GxxxIDE33
PRELIMINARY*
RDY/BSY line becomes ready again, the module may have
correctly written the data, but this is not ensured. Therefore
the data may be corrupted.
Figure 2 shows the protected module. The power is again
lost after the second sector (Sector n+1) is received,
but the internal backup power allows the sector to be
properly written, and the card completes the write sector
operation.
FIG. 2 POWER LOSS WITHOUT POWER FAILURE PROTECTION CIRCUIT
RDY/BSY
Device in Write
Process/Busy
Data Written/Device Ready
Sector Write Process
Power Loss
Data Transmitted
Sector n
Sector n+1
Sector n+2
External V
CC
Internal V
CC
Data Received
Sector n
Sector n+1
Data Written
n
n+1
Possibly Corrupted Sector
Note: Sector Blocks in these diagrams do not represent a difference with size of data written, between the data received and the data written. This represents the
shorter time to write the data than to transmit it.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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