a
FEATURES
Monolithic
12-Bit 20 MSPS A/D Converter
Low Power Dissipation: 1.4 Watts
On-Chip T/H and Reference
High Spurious-Free Dynamic Range
TTL Logic
APPLICATIONS
Radar Receivers
Digital Communications
Digital Instrumentation
Electro-Optics
ANALOG
INPUT
T/H
12-Bit 20 MSPS
Monolithic A/D Converter
AD9022
FUNCTIONAL BLOCK DIAGRAM
5-BIT
ADC
DIGITAL
12
ERROR
CORRECTION TTL
AD9022
DAC
5-BIT
ADC
ENCODE
+5V
T/H
16
DAC
4-BIT
ADC
–5.2V
GND
8
+2V
REF
PRODUCT DESCRIPTION
The AD9022 is a high speed, high performance, monolithic
12-bit analog-to-digital converter. All necessary functions, in-
cluding track-and-hold (T/H) and reference, are included
on-chip to provide a complete conversion solution. It is a
companion unit to the AD9023; the primary difference between
the two is that all logic for the AD9022 is TTL-compatible,
while the AD9023 utilizes ECL logic for digital inputs and out-
puts. Pinouts for the two parts are nearly identical.
Operating from +5 V and –5.2 V supplies, the AD9022 pro-
vides excellent dynamic performance. Sampling at 20 MSPS
with A
IN
= 1 MHz, the spurious-free dynamic range (SFDR) is
typically 76 dB; with A
IN
= 9.6 MHz, SFDR is 74 dB. SNR is
typically 65 dB.
The onboard T/H has a 110 MHz bandwidth and, more impor-
tantly, is designed to provide excellent dynamic performance for
analog input frequencies above Nyquist. This feature is neces-
sary in many undersampling signal processing applications, such
as in direct IF-to-digital conversion.
To maintain dynamic performance at higher IFs, monolithic
RF track-and-holds (such as the AD9100 and AD9101
Samplifier™) can be used with the AD9022 to process signals
up to and beyond 70 MHz.
With DNL typically less than 0.5 LSB and 20 ns transient re-
sponse settling time, the AD9022 provides excellent results
when low-frequency analog inputs must be oversampled (such
as CCD digitization). The full scale analog input is
±
1 V with a
300
Ω
input impedance. The analog input can be driven directly
from the signal source, or can be buffered by the AD96xx series
of low noise, low distortion buffer amplifiers.
All timing is internal to the AD9022; the clock signal initiates
the conversion cycle. For best results, the encode command
should contain as little jitter as possible. High speed layout
practices must be followed to ensure optimum A/D perfor-
mance.
The AD9022 is built on a trench isolated bipolar process and
utilizes an innovative multipass architecture (see the block
diagram). The unit is packaged in 28-lead ceramic DIPs and
gullwing surface mount packages. The AD9022 is specified to
operate over the industrial (–25°C to +85°C) and military
(–55°C to +125°C) temperature ranges.
Samplifier is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD9022–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter (Conditions)
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Offset Error
Gain Error
Thermal Noise
ANALOG INPUT
Input Voltage Range
Input Resistance
Input Capacitance
Analog Bandwidth
SWITCHING PERFORMANCE
1
Minimum Conversion Rate
Maximum Conversion Rate
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Output Delay (t
OD
)
ENCODE INPUT
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulsewidth (High)
Pulsewidth (Low)
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Harmonic Distortion
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
Signal-to-Noise Ratio
2
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
Signal-to-Noise Ratio
2
(Without Harmonics)
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
+25°C
Full
+25°C
Full
Full
+25°C
Full
+25°C
Full
+25°C
I
VI
I
VI
VI
I
VI
I
VI
V
Temp
(+V
S
= +5 V; –V
S
= –5.2 V; Encode = 20 MSPS, unless otherwise noted)
Test
Level
AD9022AQ/AZ
Min Typ Max
12
0.75
1.0
1.3 2.5
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
±
1.024
300 360
5
110
0.6
AD9022BQ/BZ
Min Typ Max
12
0.5
1.0
1.3 2.0
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
±
1.024
300 360
5
110
0.4
AD9022SQ/SZ
Min Typ Max
12
0.75
1.0
1.3 2.5
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
±
1.024
300 360
5
110
0.6
Units
Bits
LSB
LSB
LSB
LSB
mV
mV
% FS
% FS
LSB, rms
V
Ω
pF
MHz
MSPS
MSPS
ns
ps, rms
ns
Full
+25°C
+25°C
+25°C
Full
+25°C
+25°C
Full
IV
V
V
IV
VI
IV
V
VI
240
240
240
4
20
0.55 0.71 0.85
6
15
27.5
TTL
4
20
0.55 0.71 0.85
6
15
27.5
TTL
2.0
4
20
0.55 0.71 0.85
6
15
27.5
TTL
2.0
Full
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
VI
VI
VI
VI
V
IV
IV
V
V
I
V
V
I
V
I
V
V
I
V
2.0
8
8
6
22.5
20
20
20
65
73
70
73
72
68
64
63
64
63
62
0.8
20
20
125
125
8
8
6
22.5
20
20
20
70
75
72
75
74
72
66
65
66
65
63
0.8
20
20
125
125
22.5
20
8
8
6
0.8
20
20
125
125
V
V
µA
µA
pF
ns
ns
ns
ns
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
dB
20
20
65
73
70
73
72
68
64
63
64
63
62
63
69
63
62
64
62
61
63
61
+25°C
Full
+25°C
+25°C
Full
I
V
V
I
V
63
62
66
64
66
65
63
65
64
67
66
66
66
65
63
62
66
64
66
65
63
dB
dB
dB
dB
dB
–2–
REV. B
AD9022
Parameter (Conditions)
Two-Tone Intermodulation
Distortion Rejection
3
DIGITAL OUTPUTS
1
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
POWER SUPPLY
+V
S
Supply Voltage
+V
S
Supply Current
–V
S
Supply Voltage
–V
S
Supply Current
Power Dissipation
Power Supply
Rejection Ratio (PSRR)
4
Temp
+25°C
Test
Level
V
AD9022AQ/AZ
Min Typ Max
74
TTL
Full
Full
VI
VI
2.4
0.5
Offset Binary
4.75 5.0
100
–5.45 –5.2
180
1.4
32
2.4
0.5
Offset Binary
5.25
120
–4.95
220
1.9
AD9022BQ/BZ
Min Typ Max
74
TTL
2.4
0.5
Offset Binary
4.75 5.0
100
–5.45 –5.2
180
1.4
32
5.25
120
–4.95
220
1.9
AD9022SQ/SZ
Min Typ Max
74
TTL
V
V
Units
dBc
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
V
5.25 4.75 5.0
120
100
–4.95 –5.45 –5.2
220
180
1.9
1.4
32
mA
mA
mA
mA
W
mV/V
NOTES
1
AD9022 load is a single LS latch.
2
RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle.
3
Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.
4
PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.
Specifications subject to change without notice.
N
ANALOG
IN
t
a
t
a
= 0.7 TYPICAL
N+1
N+2
ENCODE
t
OD
t
OD
= 15–27.5 TYPICAL
DATA
OUTPUT
N–3
N–2
N–1
N
AD9022 Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
Q-28
Z-28
Q-28
Z-28
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V
S
to 0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C
AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction Temperature
2
. . . . . . . . . . . . . . . . +175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances: “Q” Package (Ceramic DIP):
θ
JC
= 10°C/W;
θ
JA
=
35°C/W. “Z” Package (Gullwing Surface Mount):
θ
JC
= 13°C/W;
θ
JA
= 45°C/W.
AD9022AQ/BQ –25°C to +85°C
AD9022AZ/BZ –25°C to +85°C
AD9022SQ
AD9022SZ
28-Lead Ceramic DIP
28-Pin Ceramic
Leaded Chip Carrier
–55°C to +125°C 28-Lead Ceramic DIP
–55°C to +125°C 28-Pin Ceramic
Leaded Chip Carrier
REV. B
–3–
AD9022
EXPLANATION OF TEST LEVELS
Test Level
PIN FUNCTION DESCRIPTIONS
Pin No.
1–3
4
5
6
7
8
Name
D3–D1
D0 (LSB)
NC
+V
S
GND
ENCODE
Function
Digital output bits of ADC; TTL
compatible.
Least significant bit of ADC output;
TTL compatible.
No Connection Internally
+5 V Power Supply
Ground
Encode clock input to ADC. Internal
T/H is placed in hold mode (ADC is
encoding) on rising edge of encode
signal.
Ground
+5 V Power Supply
Ground
Noninverting input to T/H amplifier.
–5.2 V Power Supply
+5 V Power Supply
–5.2 V Power Supply
Ground
Should be connected to –V
S
through
0.1
µF
capacitor.
I
– 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and character-
ization testing for industrial devices.
9
DIE LAYOUT AND MECHANICAL INFORMATION
10
11
12
13
14
15
16
17
18
19–25
26
27
28
GND
+V
S
GND
A
IN
–V
S
+V
S
–V
S
GND
COMP
Die Dimensions . . . . . . . . . . . . . . . . 205
×
228
×
21 (± 1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
×
4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
D11 (MSB) Most significant bit of ADC output;
TTL compatible.
D10–D4
+V
S
–V
S
GND
Digital output bits of ADC; TTL
compatible.
+5 V Power Supply
–5.2 V Power Supply
Ground
PIN DESIGNATIONS
D3
1
D2
2
D1
3
D0 (LSB)
4
NC
5
+V
S
6
28
GND
27
–V
S
26
+V
S
25
D4
24
D5
AD9022
23
D6
TOP VIEW
22
D7
(Not to Scale)
21
D8
ENCODE
8
GND
7
GND
9
+V
S 10
GND
11
A
IN 12
–V
S 13
+V
S 14
20
D9
19
D10
18
D11(MSB)
17
COMP
16
GND
15
–V
S
NC = NO CONNECT
COMPENSATION (PIN 17) SHOULD BE
CONNECTED TO –V
S
THROUGH 0.01 F
–4–
REV. B
AD9022
DEFINITIONS OF SPECIFICATIONS
+V
S
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is
reduced by 3 dB.
Aperture Delay
+V
S
The delay between the rising edge of the ENCODE command
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
ANALOG
INPUT
180
120
10pF
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
–V
S
The deviation of any code from an ideal 1 LSB step.
Harmonic Distortion
Analog Input
+V
S
100
ENCODE
900
The rms value of the fundamental divided by the rms value of
the worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” de-
termined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency tested drops by no more than 3 dB below the guaran-
teed limit.
Maximum Conversion Rate
–V
S
Encode Input
COMPENSATION
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the EN-
CODE command and the time when all output data bits are
within valid logic levels.
Overvoltage Recovery Time
50
–V
S
The amount of time required for the converter to recover to
12-bit accuracy after an analog input signal 150% of full scale is
reduced to the full-scale range of the converter.
Power Supply Rejection Ratio (PSRR)
20pF
–V
S
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise Ratio (SNR)
Compensation
+V
S
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral compo-
nents, including harmonics but excluding dc, with an analog
input signal 1 dB below full scale.
Signal-to-Noise Ratio (Without Harmonics)
11k
12k
DIGITAL
OUTPUT
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral compo-
nents, excluding the first five harmonics and dc, with an analog
input signal 1 dB below full scale.
Transient Response
–V
S
The time required for the converter to achieve 12-bit accuracy
when a step function is applied to the analog input.
Two-Tone Intermodulation Distortion (IMD) Rejection
Output Stage
Figure 1. Equivalent Circuits
The ratio of the power of either of two input signals to the
power of the strongest third-order IMD signal.
REV. B
–5–
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