STK15C68
8K x 8
AutoStore™
nvSRAM
High Performance CMOS
Nonvolatile Static RAM
FEATURES
• Nonvolatile Storage Without Battery Problems
• Directly Replaces 8K x 8 static RAM, Battery
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
• Store to EEPROM Initiated by Software or
AutoStore™
on Power Down
• Recall to SRAM by Software or Power Restore
• 15mA I
CC
at 200ns Cycle Time
• Unlimited Read, Write and Recall Cycles
• 1,000,000 Store Cycles to EEPROM
• 100 Year Data Retention Over Full Industrial
Temperature Range
• Commercial and Industrial Temp. Ranges
• 28 Pin 600 or 300 mil PDIP and 350 mil SOIC
DESCRIPTION
The STK15C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent, nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
EEPROM (the
STORE
operation) can take place auto-
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the
RECALL
operation) take place automatically on res-
toration of power. Initiation of STORE and RECALL
cycles can also be controlled by entering control
sequences on the SRAM inputs. The nvSRAM can be
used in place of existing 8K x 8 SRAMs and also matches
the pinout of 8k x 8 Battery Backed SRAMs, EPROMs,
and EEPROMs, allowing direct substitution while enhanc-
ing performance. There is no limit on the number of read
or write cycles that can be executed and no support cir-
cuitry is required for microprocessor interface.
BLOCK DIAGRAM
EEPROM ARRAY
128 x 512
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
STORE
STATIC RAM
ARRAY
128 x 512
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
12
A
7
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
POWER
CONTROL
RECALL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
A
12
DQ
1
DQ
2
V
SS
28 - 300 PDIP
28 - 600 PDIP
28 - 350 SOIC
PIN NAMES
A
0
A
1
A
2
A
3
A
4
A
10
G
A
0
- A
12
W
DQ
0
- DQ
7
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
E
W
E
G
V
CC
V
SS
4-61
STK15C68
ABSOLUTE MAXIMUM RATINGS
a
Voltage on input relative to V
SS
. . . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Note a:
Stresses greater than those listed under “Absolute Max-
mum Ratings” may cause permanent damage to the
device. This a stress rating only, and functional operation
of the device at conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC1b
PARAMETER
MIN
Average Current
MAX
85
80
75
6
15
4
35
32
28
3
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
-40
0.4
85
MIN
MAX
95
85
80
7
15
4
39
35
32
3
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
INDUSTRIAL
UNITS
(V
cc
= 5.0V
±
10%)
NOTES
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All inputs Don’t Care
W
≥
(V
CC
– 0.2V)
All others cycling, CMOS levels
All inputs Don’t Care
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All inputs
All inputs
I
OUT
= – 4mA
I
OUT
= 8mA
I
CC2c
I
CC3b
I
CC4c
I
SB1d
Average Current During STORE
Average V
CC
Current at t
AVAV
= 200ns
Average Current During
AutoStore™
Cycle
Average Current
(Standby, Cycling TTL Input Levels)
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
I
SB2d
I
ILK
I
OLK
SRAM READ CYCLES #1 & SRAM READ
+ .5
V
IH
Input Logic “1” Voltage
2.2
V
CC
V
IL
V
OH
V
OL
T
A
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
V
SS
– .5
2.4
0.8
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
2
4
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
5.0V
Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input rise and fall times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V
Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
480 Ohms
Output
30pF
INCLUDING
SCOPE
AND FIXTURE
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input capacitance
Output capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
255 Ohms
∆V
= 0 to 3V
∆V
= 0 to 3V
Figure 1: AC Output Loading
Note e: These parameters are guaranteed but not tested.
4-62
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLd, e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
3
5
10
0
25
25
10
3
5
MIN
MAX
25
35
MIN
STK15C68-25
STK15C68
(V
cc
= 5.0V
±
10%)
STK15C68-35
MAX
35
45
35
20
3
5
17
0
17
0
35
45
20
20
45
25
STK15C68-45
UNITS
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note f: W must be high during SRAM read cycles and low during SRAM write cycles.
Note g: I/O state assumes E, G, < V
IL
and W > V
IH
; device is continuously selected
Note h: Measured + 200mV from steady state output voltage
SRAM READ CYCLE #1 (Address Controlled)
f, g
t
AVAV
ADDRESS
5
t
AXQX
3
2
t
AVQV
DATA VALID
DQ(Data Out)
SRAM READ CYCLE #2 (E Controlled)
f
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
11
G
t
GLQX
DQ(Data Out)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
4
t
GLQV
t
GHQZ
9
ACTIVE
4-63
STK15C68
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
5
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
30
30
18
0
30
0
0
17
5
MAX
MIN
45
35
35
20
0
35
0
0
20
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK15C68-25
(V
cc
= 5.0V
±
10%)
STK15C68-35
STK15C68-45
UNITS
Note i:
Note j:
If W is low when E goes low the outputs remain in the high impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W CONTROLLED
j
t
AVAV
ADDRESS
t
ELWH
E
14
19
12
t
WHAX
t
AVWH
t
AVWL
W
t
WLWH
15
16
13
18
17
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDENCE
20
DATA VALID
t
WHDX
t
WHQX
21
SRAM WRITE CYCLE #2:
E CONTROLLED
j
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
15
13
17
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDENCE
DATA VALID
t
EHDX
16
4-64
STK15C68
AutoStore™
/ POWER-UP RECALL
SYMBOLS
NO.
Standard
22
23
24
25
26
t
RESTORE
t
STORE
t
DELAY
V
SWITCH
V
RESET e
Power Up RECALL Duration
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
1
PARAMETER
(V
cc
= 5.0V
±
10%)
STK15C68
UNITS NOTES
MIN
MAX
550
10
µs
ms
µs
4.5
3.6
V
V
k
g
g
4.0
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
AutoStore™
/ POWER UP RECALL
V
25
26
CC
5V
V
SWITCH
V
RESET
AUTOSTORE
TM
t
STORE
POWER UP RECALL
23
22
t
RESTORE
24
t
DELAY
W
DQ
(Data Out)
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
RECALL WHEN
ABOVE V
SWITCH
4-65
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