Low-Cost, 3.3V Zero Delay Buffer
NRND – Not Recommend for New Designs
The MPC962309 is a zero delay buffer designed to distribute high-speed
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and can
operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which
lock to an input clock presented on the REF pin. The PLL feedback is on-chip and
is obtained from the CLOCKOUT pad.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium
®
based
systems
Test Mode to bypass PLL (MPC962309 only. See
Table 3)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309), all Pb-free
Single 3.3 V supply
Ambient temperature range: –40C to +85C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
Not Recommend for New Designs
Use replacement part IDT2305
MPC962305
NRND
DATASHEET
MPC962305
MPC962309
EF SUFFIX
8-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751-06
EJ SUFFIX
8-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948J-01
EF SUFFIX
16-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751B-05
EJ SUFFIX
16-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948F-01
•
The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in
Table 3.
Bank
B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs
for chip and system testing purposes.
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During
this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0
A
of current draw for the device. The
PLL shuts down in one additional case as shown in
Table 3.
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this
situation, the difference between the output skews of two devices will be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to
be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information
page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and
MPC962309-1H, are available to provide faster rise and fall times of the base device.
Pentium II is a trademark of Intel Corporation.
MPC962305 REVISION 8 JANUARY 8, 2013
1
©2013 Integrated Device Technology, Inc.
MPC962305 Data Sheet
LOW-COST, 3.3V ZERO DELAY BUFFEr
Block Diagram
PLL
MUX
REF
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Pin Configuration
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
SOIC/TSSOP
Top View
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SOIC/TSSOP
Top View
1
8
2
7
3
6
4
5
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
S2
S1
CLKB1
Select Input
Decoding
CLKB2
CLKB3
CLKB4
REF
CLK2
CLK1
GND
CLKOUT
CLK4
V
DD
CLK3
Table 1. Pin Description for MPC962309
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
REF
(1)
CLKA1
(2)
CLKA2
(2)
V
DD
GND
CLKB1
(2)
CLKB2
(2)
S2
(3)
S1
(3)
CLKB3
(2)
CLKB4
(2)
GND
V
DD
CLKA3
(2)
CLKA4
(2)
CLKOUT
(2)
Description
Input reference frequency, 5 V-tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3 V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3 V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Table 2. Pin Description for MPC962305
Pin
1
2
3
4
5
6
7
8
Signal
REF
(1)
CLK2
(2)
CLK1
(2)
GND
CLK3
(2)
V
DD
CLK4
(2)
CLKOUT
(2)
Description
Input reference frequency, 5 V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3 V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
1. Weak pull-down.
2. Weak pull-down on all outputs.
MPC962305 REVISION 8 JANUARY 8, 2013
2
©2013 Integrated Device Technology, Inc.
MPC962305 Data Sheet
LOW-COST, 3.3V ZERO DELAY BUFFEr
Table 3. Select Input Decoding for MPC962309
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-State
Driven
Driven
Driven
CLOCK B1–B4
Three-State
Three-State
Driven
Driven
CLKOUT
(1)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and output.
Table 4. Maximum Ratings
Characteristics
Supply Voltage to Ground Potential
DC Input Voltage (Except Ref)
DC Input Voltage REF
Storage Temperature
Junction Temperature
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Value
0.5
to +3.9
0.5
to V
DD
+0.5
0.5
to 5.5
65
to +150
150
>2000
Unit
V
V
V
C
C
V
Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Description
Min
3.0
40
Max
3.6
85
30
10
7
Unit
V
C
pF
pF
pF
Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices
(1)
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Input LOW Voltage
(2)
Input HIGH Voltage
(2)
Input LOW Current
Input HIGH Current
Output LOW Voltage
(3)
Output HIGH Voltage
(3)
Power Down Supply Current
Supply Current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (1)
I
OH
= 12 mA (1H)
I
OH
=
8
mA (1)
I
OL
=
12
mA (1H)
REF = 0 MHz
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
25.0
35.0
A
mA
2.4
V
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
A
A
V
1. All parameters are specified with loaded outputs.
2. REF input has a threshold voltage of V
PP
/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MPC962305 REVISION 8 JANUARY 8, 2013
3
©2013 Integrated Device Technology, Inc.
MPC962305 Data Sheet
LOW-COST, 3.3V ZERO DELAY BUFFEr
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices
(1)
Parameter
t
1
Name
Output Frequency
Duty Cycle
(2)
= t
2
t
1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Rise Time
(2)
Fall Time
(2)
Output to Output Skew
(2)
Delay, REF Rising Edge to
CLKOUT Rising Edge
(2)
Delay, REF Rising Edge to
CLKOUT Rising Edge
(2)
Test Conditions
30-pF load
10-pF load
Measured at 1.4 V, F
OUT
= 66.67 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2. Measured in PLL Bypass Mode,
MPC962309 device only
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
Min
10
10
40.0
Typ
Max
100
133.33
Unit
MHz
MHz
%
ns
ns
ps
ps
ns
ps
ps
ms
50.0
60.0
2.50
2.50
250
0
1
5
0
350
8.7
700
200
1.0
Device to Device Skew
(2)
Cycle to Cycle Jitter
(2)
PLL Lock Time
(2)
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices
(1)
Parameter
t
1
Name
Output Frequency
Duty Cycle
(2)
= t2
t1
Duty Cycle
(2)
= t2
t1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
8
t
J
t
LOCK
Rise Time
(2)
Fall Time
(2)
Output to Output Skew
(2)
Delay, REF Rising Edge to
CLKOUT Rising
CLKOUT Rising
Edge
(2)
Measured at V
DD
/2. Measured in PLL Bypass Mode,
MPC962309 device only
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured between 0.8 V and 2.0 V using Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
1
200
1.0
0
700
ps
V/ns
ps
ms
1
5
8.7
ns
Edge
(2)
Delay, REF Rising Edge to
Device to Device Skew
(2)
Output Slew Rate
(2)
Cycle to Cycle Jitter
(2)
PLL Lock Time
(2)
30-pF load
10-pF load
Measured at 1.4 V, F
OUT
= 66.67 MHz
Measured at 1.4 V, F
OUT
< 50 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
Measured at V
DD
/2
0
Test Conditions
Min
10
10
40.0
45.0
50.0
55.0
Typ
Max
100
133.33
60.0
55.0
1.50
1.50
250
350
Unit
MHz
MHz
%
%
ns
ns
ps
ps
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MPC962305 REVISION 8 JANUARY 8, 2013
4
©2013 Integrated Device Technology, Inc.
MPC962305 Data Sheet
LOW-COST, 3.3V ZERO DELAY BUFFEr
APPLICATIONS INFORMATION
V
CC
1.4 V
GND
V
CC
1.4 V
GND
t
5
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
t
6
FB_IN
CCLK
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
Figure 1. Output-to-Output Skew t
SK(O)
Figure 2. Static Phase Offset Test Reference
V
CC
1.4 V
GND
t
2
t
1
DC = t
2
/t
1
x 100%
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
DEVICE 1
V
CC
V
CC
2
GND
DEVICE 2
V
CC
V
CC
2
GND
t
7
Figure 3. Output Duty Cycle (DC)
Figure 4. Device-to-Device Skew
V
CC
= 3.3 V
t
N
t
N+1
t
J
=
|t
N
–t
N+1
|
2.0
0.8
t
4
t
3
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
Figure 6. Output Transition Time Test Reference
MPC962305 REVISION 8 JANUARY 8, 2013
5
©2013 Integrated Device Technology, Inc.
京公网安备 11010802033920号
EEWORLD
