Low Power Consumption CMOS Regulators
In recent years, along with rising demand for low power consumption sets, demand has also been rising for low power
consumption regulators that supply power.
NEC Electronics has adopted CMOS process technology to develop low power consumption regulators.
*Under development (as of December 2006)
Features
•
High current power supply ICs in line with growing capacity requirements of LSIs:
μPD121A10
(2.0A),
μPD121WxxA
(1.5A),
μPD12115
(1.0A)
•
Equipped with on-chip on/off function and having a 1
μA
circuit current when off:
μPD121A10, μPD121WxxA, μPD12115
•
Dual power supply input system contributing to low power consumption:
μPD121A10
Applications
•
Core power supply for 90 nm process ASICs (e.g., NEC Electronics CB-90):
μPD121A10
•
General-purpose power supplies for low voltage LSIs:
μPD121WxxA, μPD12115
•
Suited for use with digital home appliances, such as printers and DVD recorders.
Package Drawing
TO-252 5pin
6.7 MAX.
10.4 MAX.
Details of dual power supply input system (μPD121A10)
Voltage difference between the INPUT and OUTPUT pins can be minimized by
dividing the power supply into two parts.
I
O
=2A
V
IN
1.8V
V
DD
5.0V
V
OUT
1.0V
6
12345
Divides the power
supply into an input
(V
IN
) for obtaining
output (V
OUT
), and
into a bias voltage
(V
DD
) for IC operation.
2.4 MAX.
GND
Standard
Start
GND
Product Specifications
Product
μPD121A10T1F
μPD121W33AT1F
μPD121W25AT1F
μPD121W18AT1F
μPD121W00AT1F
μPD12115T1F
Output
Current
(A)
2.0
1.5
1.5
1.5
1.5
1.0
Output
Voltage
(V)
0.95~1.15
Variable
3.3
Fixed
2.5
Fixed
1.8
Fixed
1.8~3.3
Variable
1.5
Fixed
Input
Stability
(mV)
MAX.
Load
Stability
(mV)
MAX.
On/Off
Function
provided
provided
provided
provided
provided
provided
Circuit Current Circuit Current I/O Voltage Ripple
(μA)
When Off Difference Rejection Package
@I
O
=0A
MAX.
(μA)
MAX.
(V)
TYP.
(dB)
@1KHz
15
33
25
18
1%
15
15
33
25
18
1%
15
500
300
300
300
300
300
1
1
1
1
1
1
0.4
@I
O
=1.0A
0.6
@I
O
=1.5A
0.6
@I
O
=1.5A
0.6
@I
O
=1.5A
0.6
@I
O
=1.5A
0.6
@I
O
=1.0A
60
56
58
60
56
60
TO-252
5pin
TO-252
5pin
TO-252
5pin
TO-252
5pin
TO-252
5pin
TO-252
5pin
Examine the data sheet carefully before using this device for designing.
NEC Electronics
Website: www.necel.com
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to
noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input
level passes through the area between V
IL
(MAX) and V
IH
(MIN).
2 HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged
separately for each device and according to related specifications governing the device.
3 PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be
used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.
4 STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation
must be executed immediately after power-on for devices with reset functions.
5 POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the
internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off
sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an
abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.
6 INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may
cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
•
•
•
•
•
•
The information in this document is current as of March 2007. The information is subject to change without notice. For actual
design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of
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(1)
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(Note)
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M8E 02. 11-1
Document No. G18465EJ1V1PF00 CP(K)
Date Published March 2007 N
©
NEC Electronics Corporation 2006
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