W986416CH-7 datasheet, PDF - EEWORLD Datasheet

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W986416CH-7: DescriptionSynchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size2MB，42 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W986416CH-7 Overview

Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54

W986416CH-7 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Winbond Electronics Corporation
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	not_compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.115 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

W986416CH-7 Preview

W986416CH

1M x 16 bit x 4 Banks SDRAM

Features

•

3.3V±0.3V power supply

Up to 166 MHz clock frequency

1,048,576 words x 4 banks x 16 bits organization

Auto Refresh and Self Refresh

CAS latency: 2 and 3

Burst Length: 1, 2, 4, 8 , and full page

Burst read, Single Writes Mode

Byte data controlled by UDQM and LDQM

Power-Down Mode

Auto-Precharge and controlled precharge

4k refresh cycles / 64ms

Interface: LVTTL

Package: TSOP II 54 pin, 400 mil - 0.80

General Description

W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x

16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M

bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts

can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3

specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of

1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated

by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock

cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst

to maximize its performance. W986416CH is ideal for main memory in high performance applications.

Key Parameters

Symbol

t

CK

t

AC

t

RP

t

RCD

I

CC1

I

CC4

I

CC6

Description

Clock Cycle Time

Access Time from CLK

Precharge to Active Command

Active to Read/Write Command

Operation Current ( Single bank )

Burst Operation Current

Self-Refresh Current

min/max

min

max

min

max

-6

6ns

5ns

18ns

80mA

130mA

1mA

-7

7ns

5.4ns

20ns

65mA

115mA

1mA

-75(PC133)

7.5ns

5.4ns

20ns

65mA

115mA

1mA

-8H(PC100)

8ns

6ns

20ns

60mA

110mA

1mA

Revision 1.2

-1-

Publication Release Date: June, 1999

W986416CH

1M x 16 bit x 4 Banks SDRAM

BLOCK DIAGRAM

CLK

CLOCK

BUFFER

CKE

CS

RAS

CAS

DECODER

CONTROL

SIGNAL

GENERATOR

COMMAND

COLUMN DECODER

WE

ROW DECODER

COLUMN DECODER

A10

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

A0

ADDRESS

BUFFER

A9

A11

BS0

BS1

MODE

REGISTER

SENSE AMPLIFIER

DMn

DATA CONTROL

CIRCUIT

DQ

BUFFER

DQ0

DQ15

REFRESH

COUNTER

COLUMN

COUNTER

UDQM

LDQM

COLUMN DECODER

ROW DECODER

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE:

The cell array configuration is 4096 * 256 * 16.

Revision 1.2

-2-

Publication Release Date: June, 1999

W986416CH

1M x 16 bit x 4 Banks SDRAM

Pin Assignment

Pin Number

23 ~ 26, 22,

29 ~35

20, 21

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,

47, 48, 50,

51, 53

19

Pin Name

A0~ A11

BS0, BS1

DQ0 ~

DQ15

Function

Address

Bank Select

Data Input/

Output

Description

Multiplexed pins for row and column address.

Row address: A0 ~ A11. Column address: A0 ~ A7.

Select bank to activate during row address latch time, or bank to

read/write during address latch time.

Multiplexed pins for data output and input.

CS#

Chip Select

18

17

16

39, 15

RAS#

CAS#

WE#

UDQM/

LDQM

CLK

CKE

Row Address

Strobe

Column

Address Strobe

Write Enable

input/output

mask

Clock Inputs

Clock Enable

Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

Command input. When sampled at the rising edge of the clock,

RAS#, CAS# and WE# define the operation to be executed.

Referred to RAS#

The output buffer is placed at Hi-Z (with latency of 2) when DQM

is sampled high in read cycle. In write cycle, sampling DQM

high will block the write operation with zero latency.

System clock used to sample inputs on the rising edge of clock.

CKE controls the clock activation and deactivation. When CKE

is low, Power Down mode, Suspend mode, or Self Refresh

mode is entered.

Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside DRAM.

Separated power from V

CC

, used for output buffers to improve

noise.

Separated ground from V

SS

, used for output buffers to improve

noise.

No connection

38

37

1, 14, 27

28, 41, 54

3, 9, 43, 49

6, 12, 46, 52

36, 40

V

CC

V

SS

V

CC

Q

V

SS

Q

NC

Power ( +3.3 V )

Ground

Power ( + 3.3 V

) for I/O buffer

Ground for I/O

buffer

No Connection

Revision 1.2

-3-

Publication Release Date: June, 1999

W986416CH

1M x 16 bit x 4 Banks SDRAM

Pin Assignment (Top View)

V

CC

DQ0

V

CC

Q

DQ1

DQ2

V

SS

Q

DQ3

DQ4

V

CC

Q

DQ5

DQ6

V

SS

Q

DQ7

V

CC

LDQM

WE

CAS

RAS

CS

BS0

BS1

A10/AP

A0

A1

A2

A3

V

CC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ15

V

SS

Q

DQ14

DQ13

V

CC

Q

DQ12

DQ11

V

SS

Q

DQ10

DQ9

V

CC

Q

DQ8

V

SS

NC

UDQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

Revision 1.2

-4-

Publication Release Date: June, 1999

W986416CH

1M x 16 bit x 4 Banks SDRAM

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

IN

,V

OUT

V

CC

,V

CC

Q

T

OPR

T

STG

T

SOLDER

P

D

I

OUT

ITEM

Input, Output Voltage

Power Supply Voltage

Operating Temperature

Storage Temperature

Soldering Temperature(10s)

Power Dissipation

Short Circuit Output Current

RATING

-0.3~V

CC

+0.3

-0.3~4.6

0~70

-55~150

260

1

50

UNIT

V

°C

W

mA

NOTES

1

RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70

°C

)

SYMBOL

V

CC

V

CC

Q

V

IH

V

IL

PARAMETER

Power Supply Voltage

Power Supply Voltage (for I/O Buffer)

Input High Voltage

Input Low Voltage

MIN

3.0

2.0

-0.3

TYP

3.3

-

MAX

3.6

V

CC

+0.3

0.8

UNIT

V

NOTES

2

Note:

V

IH

(max) = V

CC

/V

CC

Q+1.2V for pulse width < 5ns

V

IL

(min) = V

SS

/V

SS

Q-1.2V for pulse width < 5ns

CAPACITANCE (V

CC

=3.3V, Af = 1MHz, Ta=25°C)

SYMBOL

C

I

C

O

PARAMETER

Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE)

Input Capacitance (CLK)

Input/Output capacitance

MIN

-

MAX

4

6.5

UNIT

pf

Note: These parameters are periodically sampled and not 100% tested.

Revision 1.2

-5-

Publication Release Date: June, 1999

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W986416CH-7 Related Products

	W986416CH-7	W986416CH-6	W986416CH-8H
Description	Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54
Is it lead-free?	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	0.400 INCH, 0.80 MM PITCH, TSOP2-54	TSOP2, TSOP54,.46,32
Contacts	54	54	54
Reach Compliance Code	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	5 ns	6 ns
Maximum clock frequency (fCLK)	143 MHz	166 MHz	125 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	e0	e0
length	22.22 mm	22.22 mm	22.22 mm
memory density	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	54	54	54
word count	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	4MX16	4MX16	4MX16
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.001 A	0.001 A	0.001 A
Maximum slew rate	0.115 mA	0.155 mA	0.11 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	10.16 mm	10.16 mm

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