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FEATURES
Single 2.7 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
150 MSPS Input Data Rate
63.3 MHz Reconstruction Passband @ 150 MSPS
75 dBc SFDR @ 25 MHz
2 Interpolation Filter with High or Low Pass Response
73 dB Image Rejection with 0.005 dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF
Performance
Internal 2 /4 Clock Multiplier
205 mW Power Dissipation; 13 mW with Power-Down
Mode
48-Lead LQFP Package
APPLICATIONS
Communication Transmit Channel
WCDMA Base Stations, Multicarrier Base Stations,
Direct IF Synthesis
Instrumentation
14-Bit, 150 MSPS TxDAC+
™
with 2 Interpolation Filter
AD9772
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD
MOD0 MOD1
RESET
PLLLOCK
DIV0 DIV1
AD9772
CLK+
CLK–
1
1 /2
CLOCK DISTRIBUTION
AND MODE SELECT
FILTER
CONTROL
MUX
CONTROL
2 /4
PLL CLOCK
MULTIPLIER
PLLCOM
LPF
PLLVDD
OBS
PRODUCT DESCRIPTION
DATA
INPUTS
(DB13...DB0)
EDGE-
TRIGGERED
LATCHES
2 FIR
INTERPOLATION
FILTER
ZERO
STUFF
MUX
IOUTA
14-BIT DAC
IOUTB
REFIO
FSADJ
SLEEP
+1.2V REFERENCE
AND CONTROL AMP
The AD9772 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for baseband or IF waveform
reconstruction applications requiring exceptional dynamic range.
Manufactured on an advanced CMOS process, it integrates a
complete, low distortion 14-bit DAC with a 2× digital interpola-
tion filter and clock multiplier. The on-chip PLL clock multi-
plier provides all the necessary clocks for the digital filter and the
14-bit DAC. A flexible differential clock input allows for a single-
ended or differential clock driver for optimum jitter performance.
For baseband applications, the 2× digital interpolation filter
provides a low pass response, hence providing up to a three-fold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper inband
image by more than 73 dB. For direct IF applications, the 2×
digital interpolation filter response can be reconfigured to select
the upper inband image (i.e., high pass response) while sup-
pressing the original baseband image. To increase the signal
level of the higher IF images and their passband flatness in di-
rect IF applications, the AD9772 also features a “zero stuffing”
option in which the data following the 2× interpolation filter is
upsampled by a factor of two by inserting midscale data samples.
The AD9772 can reconstruct full-scale waveforms with band-
widths as high as 63.3 MHz while operating at an input data rate of
150 MSPS. The 14-bit DAC provides differential current out-
puts to support differential or single-ended applications. A
TxDAC+ is a trademark of Analog Devices, Inc.
OLE
TE
DCOM
DVDD
ACOM
AVDD
REFLO
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current out-
puts may be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an ap-
propriate resistive load.
The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772 can be
driven by the on-chip reference or by a variety of external refer-
ence voltages. The full-scale current of the AD9772 can be
adjusted over a 2 mA to 20 mA range, thus providing additional
gain ranging capabilities.
The AD9772 is available in a 48-lead LQFP package and speci-
fied for operation over the industrial temperature range of –40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. A flexible, low power 2× interpolation filter supporting re-
construction bandwidths of up to 63.3 MHz can be config-
ured for a low or high pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.
2. A “zero-stuffing” option enhances direct IF applications.
3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
4. The AD9772 digital interface, consisting of edge-triggered
latches and a flexible differential or single-ended clock input,
can support input data rates up to 150 MSPS.
5. On-chip PLL clock multiplier generates all of the internal high
speed clocks required by the interpolation filter and DAC.
6. The current output(s) of the AD9772 can easily be configured
for various single-ended or differential circuit topologies.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9772–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Monotonicity (12-Bit)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
(T
MIN
to T
MAX
, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, I
OUTFS
= 20 mA, unless otherwise
noted)
Min
14
±
3.5
±
2.0
Guaranteed Over Specified Temperature Range
–0.025
–2
–5
–1.0
200
3
1.14
1.20
1
1.26
+0.025
+2
+5
+1.25
Typ
Max
Units
Bits
LSB
LSB
OBS
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (REFLO = 3 V)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
±
0.5
±
1.5
20
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
µA
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (I
AVDD
)
Analog Supply Current in SLEEP Mode (I
AVDD
)
PLLVDD
4
Voltage Range
PLL Clock Multiplier Supply Current (I
PLLVDD
)
CLKVDD
Voltage Range
Clock Supply Current (I
CLKVDD
)
DVDD
5
Voltage Range
Digital Supply Current (I
DVDD
)
Nominal Power Dissipation
5
Power Supply Rejection Ratio (PSRR)
6
– AVDD
Power Supply Rejection Ratio (PSRR)
6
– DVDD
OPERATING RANGE
OLE
TE
0.1
1.25
10
0.5
V
MΩ
MHz
0
±
50
±
100
±
50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
2.7
3.0
34
4.3
3.0
4.5
3.0
5.5
3.0
29
205
3.6
37
6
3.6
6
3.6
7
3.6
33
231
+0.6
+0.025
+85
V
mA
mA
V
mA
V
mA
V
mA
mW
% of FSR/V
% of FSR/V
°C
2.7
2.7
2.7
–0.6
–0.025
–40
NOTES
1
Measured at IOUTA driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32× the I
REF
current.
3
Use an external amplifier to drive any external load.
4
Measured at f
DATA
= 100 MSPS and f
OUT
= 1 MHz, PLLVDD = 3.0 V.
5
Measured at f
DATA
= 50 MSPS and f
OUT
= 1 MHz.
6
Measured over a 2.7 V to 3.6 V range.
Specifications subject to change without notice.
–2–
REV. 0
AD9772
DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (f
DAC
)
Output Settling Time (t
ST
) (to 0.025%)
Output Propagation Delay
1
(t
PD
)
Output Rise Time (10% to 90%)
2
Output Fall Time (10% to 90%)
2
Output Noise (I
OUTFS
= 20 mA)
AC LINEARITY–BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (f
OUT
= 0 dBFS)
f
DATA
= 65 MSPS; f
OUT
= 1.01 MHz
f
DATA
= 65 MSPS; f
OUT
= 10.01 MHz
f
DATA
= 65 MSPS; f
OUT
= 26.01 MHz
f
DATA
= 150 MSPS; f
OUT
= 2.02 MHz
f
DATA
= 150 MSPS; f
OUT
= 20.02 MHz
f
DATA
= 150 MSPS; f
OUT
= 52.02 MHz
Two-Tone Intermodulation (IMD) to Nyquist (f
OUT1
= f
OUT2
= –6 dBFS)
f
DATA
= 65 MSPS; f
OUT1
= 5.01 MHz; f
OUT2
= 6.01 MHz
f
DATA
= 65 MSPS; f
OUT1
= 15.01 MHz; f
OUT2
= 17.51 MHz
f
DATA
= 65 MSPS; f
OUT1
= 24.1 MHz; f
OUT2
= 26.2 MHz
f
DATA
= 150 MSPS; f
OUT1
= 10.02 MHz; f
OUT2
= 12.02 MHz
f
DATA
= 150 MSPS; f
OUT1
= 30.02 MHz; f
OUT2
= 35.02 MHz
f
DATA
= 150 MSPS; f
OUT1
= 48.2 MHz; f
OUT2
= 52.4 MHz
Total Harmonic Distortion (THD)
f
DATA
= 50 MSPS; f
OUT
= 1.0 MHz; 0 dBFS
f
DATA
= 65 MSPS; f
OUT
= 10.01 MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
f
DATA
= 65 MSPS; f
OUT
= 16.26 MHz; 0 dBFS
f
DATA
= 100 MSPS; f
OUT
= 25.1 MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing
IF = 16 MHz, f
DATA
= 65.536 MSPS
IF = 32 MHz, f
DATA
= 131.072 MSPS
Four-Tone Intermodulation
15.6 MHz, 15.8 MHz, 16.2 MHz and 16.4 MHz at –12 dBFS
f
DATA
= 65 MSPS, Missing Center
AC LINEARITY–IF MODE
Four-Tone Intermodulation at IF = 70 MHz
68.1 MHz, 69.3 MHz, 71.2 MHz and 72.0 MHz at –20 dBFS
f
DATA
= 52 MSPS, f
DAC
= 208 MHz
NOTES
1
Propagation delay is delay from CLK input to DAC update.
2
Measured single-ended into 50
Ω
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +3 V, CLKVDD = +3 V, DVDD = +3 V, PLLVDD = 0 V, I
OUTFS
= 20 mA,
Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted)
Min
400
11
17
0.8
0.8
50
Typ
Max
Units
MSPS
ns
ns
ns
ns
pA/√Hz
OBS
OLE
TE
82
72
66
80
78
71
dBc
dBc
dBc
dBc
dBc
dBc
–78
–77
dB
dB
74
69
dB
dB
78
68
88
dBc
dBc
dBFS
77
dBFS
82
79
74
82
81
73
dBc
dBc
dBc
dBc
dBc
dBc
REV. 0
–3–
AD9772–SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
1
Logic “0” Current
Input Capacitance
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
(T
MIN
to T
MAX
, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, I
OUTFS
= 20 mA, unless
otherwise noted)
Min
2.1
–10
–10
5
0
0.75
0.5
1.0
2.5
1.5
1.0
2.5
1.5
3
2.25
Typ
3
0
Max
Units
V
V
µA
µA
pF
V
V
V
ns
ns
ns
ns
ns
ns
ns
0.9
+10
+10
OBS
PLL CLOCK ENABLED—FIGURE 1a
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
PLL CLOCK DISABLED—FIGURE 1b
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
CLK/PLLLOCK Delay (t
OD
)
Specifications subject to change without notice.
DB0–DB13
t
S
CLK+ – CLK–
t
H
t
LPW
t
PD
IOUTA
OR
IOUTB
t
ST
0.025%
1.5
1.5
NOTES
1
MOD1 and MOD0 have typical input currents of 120
µA
while SLEEP has a typical input current of 15
µA.
OLE
TE
5
DB0–DB13
t
S
t
H
PLLLOCK
t
OD
CLK+ – CLK–
t
LPW
0.025%
IOUTA
OR
IOUTB
0.025%
t
PD
t
ST
0.025%
Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled
Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled
–4–
REV. 0
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