QS7203-50P datasheet, PDF - EEWORLD Datasheet

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QS7203-50P: DescriptionFIFO, 2KX9, 50ns, Asynchronous, CMOS, PDIP28,; Categorystorage storage; File Size143KB，16 Pages; ManufacturerQuality Semiconductor Inc

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QS7203-50P Overview

FIFO, 2KX9, 50ns, Asynchronous, CMOS, PDIP28,

QS7203-50P Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Quality Semiconductor Inc
Objectid	1414097285
Reach Compliance Code	unknown
compound_id	294029521
Maximum access time	50 ns
Other features	RETRANSMIT
Maximum clock frequency (fCLK)	15 MHz
period time	65 ns
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
memory density	18432 bit
Memory IC Type	OTHER FIFO
memory width	9
Number of functions	1
Number of terminals	28
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX9
Output characteristics	3-STATE
Exportable	NO
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.005 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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QS7203, QS7204

FEATURES

•

High-Speed CMOS

High Speed CMOS

2K x

Bus Exchange

9, 4K x 9 FIFO

Buffer

Switches

Memories

•

QS3383

QS7203

QS32383

QS7204

10-ns flag and data access times

Fully asynchronous read and write

Zero fall-through time

Expandable in depth with no speed loss

TTL compatible input and output levels

Low power with industry standard pinouts

Retransmit capability

Dual-port RAM-based cell technology

Available in PDIP, SOJ, SOIC, and PLCC

DESCRIPTION

The QS7203 and QS7204 are 2K x 9 and 4K x 9 FIFOs, respectively. These FIFOs use a dual-port RAM-based

architecture and have independent read and write pointers. This allows high speed with zero fall-through time.

The read and write pointers are incremented on the rising edges of the read and write lines. The flag circuitry

is based on a patented high-speed design, giving precise half-full, full, and empty conditions. These flags also

prevent the FIFO from being written into when full or being read from when empty. These FIFOs are easily

cascadable to any depth and expandable to any width without any speed penalty. Retransmit resets the read

pointer to memory location zero and is useful for data communications, digital filtering, and video line-doubling

applications.

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

DATA IN

D8-D0

WRITE

CONTROL

READ

CONTROL

RESET

LOGIC

EXPANSION

LOGIC

WRITE

POINTER

READ

POINTER

DUAL-PORT

RAM ARRAY

2K x 9

4K x 9

FLAG

LOGIC

DATA OUT

Q8-Q0

Note:

and

share the same pin, so the Half-Full flag is available only in standalone, not depth-expansion mode.

MDSF-00002-04

APRIL 28, 1995

QUALITY SEMICONDUCTOR, INC.

QS7203, QS7204

OPERATIONAL DESCRIPTION AND APPLICATION INFORMATION

The QS7203 and QS7204 are 2K x 9 and 4K x 9 FIFOs, respectively. These FIFOs use a dual-port RAM-based

architecture and have independent read and write pointers. This allows high speed with zero fall-through time.

The write line causes data to be written into the FIFO. The read line causes data to be read from the FIFO.

The read line also activates the three-state outputs to present the read data. The read and write pointers are

incremented on the rising edges of the read and write lines. The flag circuitry is based on a reliable sequential

design giving precise half-full, full, and empty conditions. These flags also prevent the FIFO from being written

into when full or being read from when empty. Depth expansion pins are provided, which allow these FIFOs

to be expanded in depth without speed penalty. Retransmit capability is provided. Activating the retransmit

pin resets the read pointer to zero and is useful for data communications and digital filtering applications.

SIGNAL DESCRIPTION

DATA INPUTS

D8-D0

The data in lines D8 to D0 provide data to be written into the FIFO.

Note:

Unused inputs must be tied to Vcc or GND.

CONTROL INPUTS

Reset (

)

The reset input resets the read and write pointers and the flags to zero. The FIFO must be reset at power-up

to ensure proper operation of the pointers and flags. This is done by asserting the reset line to a LOW state,

which causes the FIFO flags to be set to empty. This causes the Empty flag to be asserted and the Full and

Half-Full flags to be de-asserted. Read and write lines must be HIGH for t

RSS

before and t

RSR

after the rising

edge of the reset signal for a valid reset operation.

Write (

)

The write line causes data to be written into the FIFO. A write cycle is initiated by the falling edge of the write

signal. A write will occur if the Full flag was not asserted, indicative of at least one empty location in the FIFO.

Data is stored in the FIFO on the rising edge of the write signal, using the data setup and hold times specified.

Data is stored in a sequential manner in the FIFO, and the read and write operations can be asynchronous.

The falling edge of the write signal asserts the Half-Full and Full flags when the next word after half-full is written

and when the last word has been written, respectively. The rising edge of the write line de-asserts the Empty

flag when the first write is performed after an empty or reset condition. When the Full flag is asserted,

subsequent writes are blocked. The user can apply a write pulse after the full condition is de-asserted.

Read (

)

The read signal causes data to be read from the FIFO. A read cycle is initiated by the falling edge of the read

signal. A read is performed if the Empty flag is not asserted, indicative of at least one word being present in

the FIFO. The data is accessed on a first-in-first-out basis asynchronous to the write operations. After the read

control is de-asserted, the data outputs go from a valid state into high impedance. The outputs remain in high

impedance until the next read cycle. When all the data is read on the last read cycle, the Empty flag is asserted,

and will inhibit any subsequent reads. The outputs will be in high impedance for subsequent read operation

until a write occurs that de-asserts the Empty flag, allowing a read cycle to begin. The outputs may also be

in high impedance when the FIFOs are cascaded in depth. In this case, only the active FIFO asserts data, and

the other FIFO data outputs are in high impedance. The falling edge of the read signal will set the Empty flag

during the read of the last word in the FIFO. The rising edge of the read signal will de-assert the Half-Full and

the Full flags when the FIFO has reached half-full and when the FIFO is full, respectively.

MDSF-00002-04

APRIL 28, 1995

QUALITY SEMICONDUCTOR, INC.

QS7203, QS7204

First Load/ Retransmit (

)

This is a dual-purpose input. In the depth-expansion mode, this pin indicates the first FIFO device that will be

loaded or read from after a reset operation. In the standalone or width-expansion mode (when the expansion

input is grounded) this pin initiates the retransmit function.

Retransmit resets the read pointer to zero. The read and write signals must be HIGH before and after the rising

edge of the retransmit pulse. The retransmit feature is useful when the same data needs to be read again

without rewriting it into the FIFO. Pulsing the retransmit pin will cause the read pointer to be reset to zero, and

the previously read data can be read again. The flags will change according to the relative location of the

pointers after the retransmit pulse.

Expansion In (

)

This is a dual-purpose pin. When it is grounded, it indicates that the FIFO is a standalone device. When it is

not grounded, it indicates that the FIFO is in the depth-expansion mode. In the depth-expansion mode, this

pin is connected to the

pin of the previous device.

DATA OUTPUTS

Data Outputs Q8-Q0

The 9-bit data output bus Q8-Q0 receives the read data from the FIFO. It is active whenever the read signal

is LOW. It is in a high impedance state when the read signal is HIGH. It is also in high impedance when the

FIFO Empty flag is active (i.e., when the FIFO is empty).

CONTROL OUTPUTS

Full Flag (

)

The Full flag indicates that the FIFO is full. The Full flag is asserted when there is only one empty location in

the FIFO and a falling edge of the write signal initiates the last write operation. The rising edge of the read signal

de-asserts the flag, as at least one location has become available.

Empty Flag (

)

The Empty flag indicates the FIFO is empty. It is asserted when there is only one word in the FIFO, and a falling

edge of the read signal initiates the last read operation. The rising edge of the write signal de-asserts the flag,

as one word is now present in the FIFO.

Expansion Out/Half-Full Flag (

)

This is a dual-purpose flag. In the single-device mode, the expansion in (

) is grounded and the Half-Full flag

output is present on this pin. Whenever the FIFO is more than half-full, the flag remains asserted . When the

FIFO is exactly half-full, the next falling edge of the write signal asserts the flag. The rising edge of read that

causes the FIFO to be half-full will de-assert the Half-Full flag. It will remain asserted until the FIFO is half-

full or less than half-full. The name given to the flag is half-full, but it is asserted on the one plus the half-full

condition.

In the depth-expansion mode, the expansion out (

) is connected to the expansion in (

) of the next device.

This causes the next device to perform write or read operations.

QUALITY SEMICONDUCTOR, INC.

MDSF-00002-04

APRIL 28, 1995

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