Preliminary Data Sheet, Rev. 1
September 1998
ORCA
®
Series 3
Field-Programmable Gate Arrays
Features
T
High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, with a migra-
tion plan to 0.25 µm technology (4- or 5-input look-up
table delay of 1.7 ns with -5 speed grade in 0.35 µm).
Up to 186,000 usable gates in 0.3 µm, expanding to
320,000 usable gates in 0.25 µm.
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
New
twin-quad programmable function unit (PFU) archi-
tecture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
New
flexible input structure (FINS) of the PFUs provides
a routability enhancement for LUTs with shared inputs
and the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for
nibble-, byte-wide, or longer arithmetic functions, with
the
new
option to register the PFU carry-out.
New
softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
New
supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder, and
PAL*-like
AND-OR with optional INVERT in each pro-
grammable logic cell (PLC).
T
Abundant hierarchical routing resources based on rout-
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability: 12 mA sink/
6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (IEEE
†
1149.1 JTAG) and
3-state all I/O pins (TS_ALL) testability functions.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four
new
ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to inter-
nal general clock routing.
New
StopCLK feature to glitchlessly stop/start Express-
CLK
s
independently by user command.
New
programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)
latch for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
*
PAL
is a trademark of Advanced Micro Devices, Inc.
†
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
Series 3 FPGAs
Device
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
OR3T165
Usable Gates
‡
18K—36K
24K—48K
40K—80K
58K—116K
92K—186K
120K—244K
Max
Registers
1872
2436
3780
5412
8400
10752
Max User
RAM Bits
18K
25K
41K
62K
100K
131K
Max
User I/Os
192
224
288
352
448
512
Array Size
12 x 12
14 x 14
18 x 18
22 x 22
28 x 28
32 x 32
‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
ORCA
Series 3 FPGAs
Preliminary Data Sheet, Rev. 1
September 1998
Table of Contents
Contents
Page
Contents
Page
Features .......................................................................... 1
System-Level Features ................................................... 3
Description ...................................................................... 4
FPGA Overview .......................................................... 4
PLC Logic ................................................................... 4
PIC Logic .................................................................... 5
System Features ......................................................... 5
Routing ....................................................................... 5
Configuration .............................................................. 5
ORCA
Foundry Development System ........................ 6
Architecture ..................................................................... 6
Programmable Logic Cells .............................................. 8
Programmable Function Unit ...................................... 8
Look-Up Table Operating Modes .............................. 10
Supplemental Logic and Interconnect
Cell (SLIC) ............................................................ 18
PLC Latches/Flip-Flops ............................................ 22
PLC Routing Resources ........................................... 24
PLC Architectural Description ................................... 31
Programmable Input/Output Cells ................................ 33
5 V Tolerant I/O ......................................................... 34
PCI Compliant I/O ..................................................... 34
Inputs ........................................................................ 35
Outputs ..................................................................... 38
PIC Routing Resources ............................................ 41
PIC Architectural Description .................................... 42
High-Level Routing Resources ..................................... 44
Interquad Routing ..................................................... 44
Programmable Corner Cell Routing .......................... 45
PIC Interquad (MID) Routing .................................... 46
Clock Distribution Network ............................................ 47
PFU Clock Sources .................................................. 47
Clock Distribution in the PLC Array .......................... 48
Clock Sources to the PLC Array ............................... 49
Clocks in the PICs .................................................... 49
ExpressCLK Inputs ................................................... 50
Selecting Clock Input Pins ........................................ 50
Special Function Blocks ................................................ 51
Single Function Blocks ............................................. 51
Boundary Scan ......................................................... 54
Microprocessor Interface (MPI) .................................... 61
PowerPC
System ...................................................... 62
i960
System .............................................................. 63
MPI Interface to FPGA .............................................. 64
MPI Setup and Control ............................................. 65
Programmable Clock Manager
(PCM): (Advance Information) ....................................... 69
PCM Registers .......................................................... 70
Delay-Locked Loop (DLL) Mode ............................... 72
Phase-Locked Loop (PLL) Mode .............................. 73
PCM/FPGA Internal Interface ................................... 75
PCM Operation ......................................................... 75
PCM Detailed Programming ..................................... 76
PCM Applications ..................................................... 79
PCM Cautions ........................................................... 80
FPGA States of Operation ............................................ 81
Initialization ............................................................... 81
Configuration ............................................................ 82
Start-Up .................................................................... 83
Reconfiguration ......................................................... 84
Partial Reconfiguration .............................................. 84
Other Configuration Options ..................................... 84
Configuration Data Format ............................................ 85
Using
ORCA
Foundry to Generate
Configuration RAM Data ....................................... 85
Configuration Data Frame ......................................... 85
Bit Stream Error Checking ........................................ 87
FPGA Configuration Modes .......................................... 88
Master Parallel Mode ................................................ 88
Master Serial Mode ................................................... 89
Asynchronous Peripheral Mode ................................ 90
Microprocessor Interface (MPI) Mode ....................... 90
Slave Serial Mode ..................................................... 93
Slave Parallel Mode .................................................. 93
Daisy-Chaining .......................................................... 94
Daisy-Chaining with Boundary Scan.......................... 95
Absolute Maximum Ratings .......................................... 95
Recommended Operating Conditions ........................... 95
Electrical Characteristics ............................................... 96
Timing Characteristics ................................................... 98
Description ................................................................ 98
PFU Timing ............................................................. 100
PLC Timing ............................................................. 107
SLIC Timing ............................................................ 107
PIO Timing .............................................................. 108
Special Function Blocks Timing ...............................111
Clock Timing ........................................................... 118
Configuration Timing ............................................... 125
Readback Timing .................................................... 135
Input/Output Buffer Measurement Conditions ............. 136
Output Buffer Characteristics ...................................... 137
OR3Cxx .................................................................. 137
OR3Txxx ................................................................. 138
Estimating Power Dissipation ..................................... 139
OR3Cxx .................................................................. 139
OR3Txxx ................................................................. 140
PCM Power Dissipation ........................................... 141
Pin Information ............................................................ 142
Pin Descriptions ...................................................... 142
Package Compatibility ............................................ 146
Compatibility with OR2C/TxxA Series ..................... 147
Package Thermal Characteristics ................................ 194
ΘJA
.......................................................................... 194
ψ
JC ......................................................................... 194
ΘJC
.......................................................................... 194
ΘJB
.......................................................................... 194
FPGA Maximum Junction Temperature ................... 195
Package Coplanarity.................................................... 196
Package Parasitics ...................................................... 196
Package Outline Diagrams .......................................... 197
Terms and Definitions .............................................. 197
208-Pin SQFP.......................................................... 198
208-Pin SQFP2........................................................ 199
240-Pin SQPF.......................................................... 200
240-Pin SQFP2........................................................ 201
256-Pin PBGA.......................................................... 202
352-Pin PBGA.......................................................... 203
432-Pin EBGA.......................................................... 204
600-Pin EBGA.......................................................... 205
Index ............................................................................ 206
Ordering Information ................................................... 209
2
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
September 1998
ORCA
Series 3 FPGAs
clock phase and duty cycle for input clock rates from
5 MHz to 80 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
T
True, internal, 3-state, bidirectional buses with sim-
ple control provided by the
new
SLIC.
T
32 x 4 RAM per PFU, configurable as single- or dual-
port at >125 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the
new
SLIC decoders as bank drivers.
*
i960
is a registered trademark of Intel Corporation.
†
PowerPC
is a registered trademark of International Business
Machines Corporation.
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the
ORCA
Series 3 include:
T
Full PCI local bus compliance.
T
New
dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to
i960
* and
PowerPC
†
processors with user-configurable
address space provided.
T
New
parallel readback of configuration data capabil-
ity with the built-in microprocessor interface.
T
New
programmable clock manager (PCM) adjusts
Table 2.
ORCA
Series 3 System Performance
Parameter
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
36-bit Parity Check (internal)
1.
2.
3.
4.
5.
6.
7.
# PFUs
2
2
11.5
8
15
4
4
8
8
0.25
0
2
0
2
-4
68
68
23
58
85
128
157
113
113
4.87
2.35
15.05
5.90
15.05
Speed
-5
90
90
31
76
119
174
209
153
153
3.66
1.82
11.20
4.53
11.20
-6
121
121
41
104
163
235
283
208
208
2.69
1.36
8.01
3.41
8.01
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
Implemented using 32 x 4 dual-port RAM mode.
Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
Implemented in five partially occupied SLICs.
Note: Shaded values are advance information and are valid for OR3Txxx devices only.
Lucent Technologies Inc.
3
ORCA
Series 3 FPGAs
Preliminary Data Sheet, Rev. 1
September 1998
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4
single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform
PAL-like
functions. The 3-state drivers
in the SLIC and their direct connections to the PFU out-
puts make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
Description
FPGA Overview
The
ORCA
Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series from Lucent Technologies Micro-
electronics Group, with enhancements and innovations
geared toward today’s high-speed designs and tomor-
row’s systems on a single chip. Designed from the start
to be synthesis friendly and to reduce place and route
times while maintaining the complete routability of the
ORCA
2C/2T devices, Series 3 more than doubles the
logic available in each logic block and incorporates
system-level features that can further reduce logic
requirements and increase system speed.
ORCA
Series 3 devices contain many new patented enhance-
ments and are offered in a variety of packages, speed
grades, and temperature ranges.
The
ORCA
Series 3 FPGAs consist of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL-like
functions, and 3-state buffering can be per-
formed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
4
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
September 1998
ORCA
Series 3 FPGAs
Routing
The abundant routing resources of the
ORCA
Series 3
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed on
a low-skew, high-speed distribution network and may
be sourced from PLC logic, externally from any I/O
pad, or from the very fast
ExpressCLK
pins. Express-
CLKs may be glitchlessly and independently enabled
and disabled with a programmable control signal using
the new
StopCLK
feature. The improved PIC routing
resources are now similar to the patented intra-PLC
routing resources and provide great flexibility in moving
signals to and from the PIOs. This flexibility translates
into an improved capability to route designs at the
required speeds when the I/O signals have been
locked to specific pins.
Description
(continued)
PIC Logic
Series 3 PIC addresses the demand for ever-increas-
ing system clock speeds. Each PIC contains four pro-
grammable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an
ExpressCLK.
This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the
ORCA
2C/2T capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
ORCA
2C/2T Series buffer with a new, fast, open-drain
option for ease of use on system buses.
Configuration
The FPGA’s functionality is determined by internal
configuration RAM. The FPGA’s internal initialization/
configuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM or any
other storage media. Serial EEPROMs provide a sim-
ple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
System Features
Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface and its
innovative programmable clock manager. These func-
tional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in
today’s high-speed systems.
Lucent Technologies Inc.
5
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