Description
The H5TQ2G43EFR-xxC, H5TQ2G83EFR-xxC are a
2Gb
CMOS Double Data Rate III (DDR3) Synchronous
DRAM, ideally suited for the main memory applications which requires large memory density and high
bandwidth. SK hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-
width.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• 8banks
• Average Refresh Cycle (Tcase of
0
o
C~ 95
o
C)
• Differential Data Strobe (DQS, DQS)
- 7.8 µs at
0
o
C ~ 85
o
C
- 3.9
µs at 85
o
C ~ 95
o
C
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• JEDEC standard 78ball FBGA(x4/x8)
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and
14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,
10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
Rev. 1.1 / Apr. 2013
3
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