240pin DDR3L SDRAM Registered DIMM
DDR3L SDRAM Registered DIMM
Based on 2Gb C-die
HMT325R7CFR8A
HMT351R7CFR8A
HMT351R7CFR4A
HMT31GR7CFR8A
HMT31GR7CFR4A
HMT42GR7CMR4A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 /Aug. 2012
1
Revision History
Revision No.
0.1
0.2
0.3
1.0
History
Initial Release
Typo Collected
Feature list updated on page 3
Latest JEDEC Spec and
Product Line-up Updated
Draft Date
Aug.2011
Sep.2011
Oct.2011
Aug.2012
Remark
Rev. 1.0 / Aug. 2012
2
Description
SK hynix Registered DDR3L SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices.
These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as
servers and workstations.
Features
•
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•
•
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Power Supply: VDD=1.35V (1.283V to 1.45V)
VDDQ = 1.35V (1.283V to 1.45V)
VDDSPD=3.0V to 3.6V
Functionality and operations comply with the DDR3L SDRAM datasheet
8 internal banks
Data transfer rates: PC3-12800, PC3-10600, PC3-8500
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Supports ECC error correction and detection
On-Die Termination (ODT)
Temperature sensor with integrated SPD
Backward compatible with 1.5V DDR3 Memory module.
This product is in compliance with the RoHS directive.
Ordering Information
Part Number
HMT325R7CFR8A-H9/PB
HMT351R7CFR8A-H9/PB
HMT351R7CFR4A-H9/PB
HMT31GR7CFR8A-G7/H9
HMT31GR7CFR4A-H9/PB
HMT42GR7CMR4A-G7/H9
Density
2GB
4GB
4GB
8GB
8GB
16GB
Organization
256Mx72
512Mx72
512Mx72
1Gx72
1Gx72
2Gx72
Component Composition
256Mx8(H5TC2G83CFR)*9
256Mx8(H5TC2G83CFR)*18
512Mx4(H5TC2G43CFR)*18
256Mx8(H5TC2G83CFR)*36
512Mx4(H5TC2G43CFR)*36
DDP 1Gx4(H5TC4G43CMR)*36
# of
ranks
1
2
1
4
2
4
FDHS
X
X
X
O
O
O
* In order to uninstall FDHS, please contact sales administrator
Rev. 1.0 / Aug. 2012
3
Key Parameters
MT/s
DDR3L-1066
DDR3L-1333
DDR3L-1600
Grade
-G7
-H9
-PB
tCK
(ns)
1.875
1.5
1.25
CAS
Latency
(tCK)
7
9
11
tRCD
(ns)
13.125
tRP
(ns)
13.125
tRAS
(ns)
37.5
36
35
tRC
(ns)
50.625
49.5
(49.125)*
48.75
(48.125)*
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
13.5
13.5
(13.125)* (13.125)*
13.75
13.75
(13.125)* (13.125)*
*
SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz]
Grade
CL6
-G7
-H9
-PB
800
800
800
CL7
1066
1066
1066
CL8
1066
1066
1066
1333
1333
1333
1333
1600
CL9
CL10
CL11
Remark
Address Table
2GB(1Rx8)
Refresh
Method
Row Address
Column
Address
Bank Address
Page Size
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
4GB(2Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
4GB(1Rx4)
8K/64ms
A0-A14
A0-A9,A11
BA0-BA2
1KB
8GB(4Rx8)
8K/64ms
A0-A14
A0-A9
BA0-BA2
1KB
8GB(2Rx4)
8K/64ms
A0-A14
A0-A9,A11
BA0-BA2
1KB
16GB(4Rx4)
8K/64ms
A0-A14
A0-A9,A11
BA0-BA2
1KB
Rev. 1.0 / Aug. 2012
4
Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Num
ber
1
1
1
1
2
1
Pin Name
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
EVENT
TEST
RESET
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Description
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes,
Termination data strobes
Data strobes, negative line,
Termination data strobes
Reserved for optional hardware
temperature sensing
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
Register and SDRAM control pin
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
Num
ber
2
64
8
9
9
9
CAS
WE
S[3:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Err_Out
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Parity bit for the Address and
Control bus
Parity error found on the
Address and Control bus
1
1
4
14
1
1
3
1
1
3
1
1
9
1
1
1
22
59
1
1
4
1
Rev. 1.0 / Aug. 2012
5
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