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GS8162ZV36BB-250

Description
ZBT SRAM, 512KX36, 5.5ns, CMOS, PBGA119, FBGA-119
Categorystorage    storage   
File Size889KB,31 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS8162ZV36BB-250 Overview

ZBT SRAM, 512KX36, 5.5ns, CMOS, PBGA119, FBGA-119

GS8162ZV36BB-250 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeBGA
package instructionBGA,
Contacts119
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time5.5 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeR-PBGA-B119
JESD-609 codee0
length22 mm
memory density18874368 bit
Memory IC TypeZBT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals119
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX36
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.99 mm
Maximum supply voltage (Vsup)2 V
Minimum supply voltage (Vsup)1.6 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Preliminary
GS8162ZV18/36B(B/D)
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165-, or 209-Bump BGA package
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V V
DD
1.8 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162ZV18/36B(B/D) may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162ZV18/36B(B/D) is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
Functional Description
The GS8162ZV18/36B(B/D) is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
4.0
280
330
5.5
5.5
210
240
-200
3.0
5.0
230
270
6.5
6.5
185
205
-150
3.8
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.00 9/2004
1/31
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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