LXT6051 datasheet, PDF - EEWORLD Datasheet

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LXT6051: DescriptionTerminator, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208; CategoryWireless rf/communication Telecom circuit; File Size2MB，144 Pages; ManufacturerCortina Systems Inc

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LXT6051 Overview

Terminator, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208

LXT6051 Parametric

Parameter Name	Attribute value
Maker	Cortina Systems Inc
Objectid	1809646163
Parts packaging code	QFP
package instruction	FQFP,
Contacts	208
Reach Compliance Code	compliant
compound_id	6912915
JESD-30 code	S-PQFP-G208
length	28 mm
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	4.1 mm
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ATM/SONET/SDH TERMINATOR
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

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LXT6051

STM-1/0 SDH Overhead Terminator

Datasheet

The LXT6051 Overhead Terminator implements the Regenerator Section Termination,

Multiplexer Section Termination and Higher Order Path Termination in STM-0 (51Mb/s) and

STM-1 (155Mb/s) multiplexers. It provides micro-controller access for performance monitoring,

alarm detection and configuration for transmit and receive paths. When used with the

LXT6251A (21E1 Mapper), a complete solution for a 21 E1 or a 63 E1 Multiplexer is created.

The LXT6051 is compliant with the latest releases of ITU-T G.703 and G.707. It provides all the

alarm and control features to easily implement the multiplexer described in ITU-T G.783.

Product Features

SDH Terminal Mux/ADM for microwave

radio

ADM fiber ring Mux

Digital Loop Carrier (NGDLC) Systems

Digital Cross-Connect System

Performs Regenerator Section, Multiplexer

Section, and Higher Order Path Overhead

Processing for STM-1 and STM-0 signals.

Byte parallel interface for STM-1 or STM-

0, with byte alignment performed

internally. Serial NRZ or B3ZS interface

option for STM-0.

Demultiplexes STM-0/STM-1 signals to

Telecom Bus output with optional pointer

processor re-timing.

Multiplexes Telecom Bus data into STM-0

or STM-1 signals with pointer processing.

Compatible with 1+1 protected ITU

architecture.

Records all RSOH, MSOH, and HPOH

alarms. One second counters for B1, B2,

B3, M1 REI and G1 REI.

Full J0/J1 trace identifier processing.

Serial access to STM-1 user-defined,

media-dependent and national bytes.

Dedicated pins for serial access or pass-

through feature for E1, E2, F1, F2, F3, D1-

D3 & D4-D12 bytes.

Low power CMOS technology with 3.3V

core and 5V I/O in PQFP-208 package.

IEEE 1149.1 Boundary Scan (JTAG)

support.

As of January 15, 2001, this document replaces the Level One document

LXT6051 STM-1/0 SDH Overhead Terminator Datasheet.

Order Number: 249302-001

January 2001

STM-1/0 SDH Overhead Terminator — LXT6051

Contents

1.0

2.0

3.0

Block Diagram

...........................................................................................................11

Pin Assignments And Signal Description

......................................................12

Functional Description

...........................................................................................22

3.1

3.2

3.3

Transmit Data Flow .............................................................................................22

Receive Data Flow ..............................................................................................23

3.2.1 Reference Clocks ...................................................................................26

Modes of Operation.............................................................................................26

3.3.1 Chip Configuration..................................................................................26

3.3.2 Repeater Mode Configuration ................................................................26

3.3.3 Terminal Mode Configuration (No Protection) ........................................27

3.3.3.1 Receive Side Telecom Bus Timing Source ...............................28

3.3.3.2 Transmit Side Telecom Bus Timing Source ..............................28

3.3.4 Add and Drop Configuration...................................................................29

3.3.4.1 Receive Side Telecom Bus Timing Source ...............................29

3.3.4.2 Transmit Side Telecom Bus Timing Source ..............................29

3.3.4.3 Updating the Transmit AU Pointer Justification Event

Counters ....................................................................................30

3.3.5 Terminal Protection Mode ......................................................................31

3.3.5.1 Receive Side Telecom Bus Timing Source ...............................31

3.3.5.2 Transmit Side Telecom Bus Timing Source ..............................31

3.3.6 Receiver Default Operation ....................................................................31

3.3.6.1 Serial Interface ..........................................................................31

3.3.6.2 Parallel Interface .......................................................................32

3.3.6.3 Clock Distribution and Reference ..............................................34

3.3.6.4 Framer .......................................................................................34

3.3.6.5 Regenerator Section Receiver ..................................................36

3.3.6.6 Multiplexer Section Receiver .....................................................38

3.3.6.7 Multiplexer Section Protection (MSP) Block ..............................40

3.3.6.8 Pointer Recovery .......................................................................40

3.3.6.9 Higher Order Path Receiver ......................................................41

3.3.6.10Re-Timing Function ...................................................................43

3.3.7 Transmitter Default Operation ................................................................44

3.3.7.1 Higher Order Path Transmitter ..................................................44

3.3.7.2 Transmit Pointer Processing Function ......................................46

3.3.7.3 Transmit Multiplex Section Protection (MSP Block) ..................47

3.3.7.4 Multiplexer Section Transmitter .................................................47

3.3.7.5 Regenerator Section Transmitter ..............................................49

3.3.7.6 Parallel Interface .......................................................................52

3.3.7.7 Serial Interface ..........................................................................52

3.3.7.8 Clock Distribution and Reference ..............................................52

Transmit Frame Parallel Timing ..........................................................................55

Transmit Frame Serial Timing .............................................................................56

Receive Re-timing Functional Timing..................................................................57

Telecom Bus Interface ........................................................................................57

4.4.1 Multiplexer Telecom Bus Terminal Mode ...............................................57

4.0

Functional Timing

....................................................................................................55

4.1

4.2

4.3

4.4

Datasheet

LXT6051 — STM-1/0 SDH Overhead Terminator

4.5

4.6

4.4.2 Multiplexer Telecom Bus ADM Mode ..................................................... 58

4.4.3 Demultiplexer Telecom Bus (Terminal or ADM) Mode........................... 59

4.4.4 Protection Bus Interface Timing ............................................................. 62

4.4.5 Transmitter “Master” in 1+1 Protection Configuration ............................ 63

4.4.6 Transmitter “Slave” in 1+1 Protection Configuration .............................. 63

4.4.7 Receive”Master” in 1+1 Protection Configuration .................................. 63

4.4.8 Receive “Slave” Configuration (1+1 Protection)..................................... 64

4.4.9 OverHead Byte Access Timing .............................................................. 66

F2 and F3 Digital Channel Functional Timing ..................................................... 66

4.5.1 Transmit side access ............................................................................. 66

4.5.2 Receive Side Access ............................................................................. 67

4.5.3 E1, E2 and F1 Orderwire Channel Functional Timing............................ 67

4.5.3.1 Transmit Timing......................................................................... 67

4.5.3.2 Receive timing........................................................................... 68

4.5.4 HPOH Bytes Serial Access Functional Timing....................................... 68

4.5.4.1 Transmit serial HPOH Timing.................................................... 68

4.5.4.2 Receive Serial HPOH Timing .................................................... 69

4.5.5 SOH Overhead Access Functional Timing............................................. 70

4.5.5.1 Transmit Side SOH Serial Timing ............................................. 70

4.5.5.2 Receive Side SOH Serial Timing .............................................. 71

4.5.6 D1 to D3 Data Communication Channel Functional Timing................... 72

4.5.6.1 Transmit Side Access................................................................ 72

4.5.6.2 Receive Side Access................................................................. 72

4.5.7 D4 to D12 Data Communication Channel .............................................. 73

4.5.7.1 Transmit Side Access................................................................ 73

4.5.7.2 Receive Side Access................................................................. 73

BIP Receive Functional Timing ........................................................................... 74

5.0

6.0

Test Specifications

.................................................................................................. 75

Microprocessor Interface & Register Description

...................................... 91

6.1

Microcontroller Interface...................................................................................... 91

6.1.1 Intel interface.......................................................................................... 91

6.1.2 Motorola interface .................................................................................. 91

6.1.3 Interrupt Handling................................................................................... 92

6.1.3.1 Interrupt Sources....................................................................... 92

6.1.3.2 Interrupt Enables ....................................................................... 92

6.1.3.3 Interrupt Clearing....................................................................... 92

6.1.3.4 Status Registers Access ........................................................... 93

6.1.3.5 C2, K3, K2, K1 and S1 Receive Byte Registers Access ........... 93

6.1.4 Counter Reading .................................................................................... 93

Global Registers.................................................................................................. 97

6.3.1 OCR1—Operational Configuration 1 (50H)............................................ 97

6.3.2 OCR2—Operational Configuration 2 (51H)............................................ 98

6.3.3 CHIP_ID—Chip ID Number (52H).......................................................... 99

6.3.4 BUF_ACNTS—Buffer All Counters (54H) .............................................. 99

Receive Regenerator Section Termination Registers ......................................... 99

6.4.1 R_RSTC1—Receive RST Configuration 1 (40H)................................... 99

6.4.2 R_RSTC2—Receive RST Configuration 2 (47H)................................. 100

6.4.2.1 LOF_LMN—Loss of Frame L, M, & N Configuration

6.2

6.3

6.4

Datasheet

STM-1/0 SDH Overhead Terminator — LXT6051

6.5

6.6

6.7

6.8

6.9

6.10

(41–42H) .................................................................................101

6.4.3 OOF_ECNT—Out Of Frame Event Counter (44–43H) ........................101

6.4.4 B1_ERRCNT—B1 Error Counter (46–45H) .........................................101

Receive Regenerator and Multiplexer Section Termination Registers..............102

6.5.1 J0_RSTR_C—J0 Expected String Control (0EH) ................................102

6.5.2 J0_RSTR_D—J0 Expected String Data (0FH).....................................102

6.5.3 WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH)...........102

6.5.4 CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH) ....103

6.5.5 E#_EXCWIN—Number of Errs/Win for Excessively Errored Window

(1EH) ....................................................................................................103

6.5.6 WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H)............103

6.5.7 CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H)...103

6.5.8 E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored

Window (18H).......................................................................................104

6.5.9 B2_BLKCNT—B2 Block Error Counter (11–10H) ................................104

6.5.10 B2_BIPCNT—B2 BIP Error Counter (14–12H) ....................................104

6.5.11 MR_BLKCNT—MST REI Block Error Counter (0A–09H) ....................104

6.5.12 MR_BIPCNT—MST REI BIP Error Counter (0D–0BH) ........................105

6.5.13 R_K1—Received K1 byte (00H)...........................................................105

6.5.14 R_K2—Received K2 Byte (01H) ..........................................................105

6.5.15 R_S1—Received S1 byte (02H)...........................................................105

6.5.16 R_NU1_8—Received Nu1_8 byte (03H)..............................................105

6.5.17 R_NU1_9—Received Nu1_9 byte (04H)..............................................105

6.5.18 R_NU2_8—Received Nu2_8 byte (05H)..............................................106

6.5.19 R_NU2__9—Received Nu2_9 byte (06H)............................................106

6.5.19.1R_NU9_8—Received Nu9_8 byte (07H).................................106

6.5.20 R_NU9_9—Received Nu9_9 byte (08H)..............................................106

Receive Multiplexer Section Protection Registers.............................................107

6.6.1 R_MSP_C—Receive MSP Configuration (20H)...................................107

6.6.2 R_MSP_OP—Receive MSP Operational (21H) ...................................107

6.6.3 R_PROTK1—Received K1 byte on Protection Bus from Slave (22H) .107

R_PROTK2—Received K2 byte on Protection Bus from Slave (23H) ..............108

Receive Multiplexer Section Adaptation Registers............................................108

6.8.1 R_MSA_C—Receive MSA Configuration (90H)...................................108

6.8.2 R_AU_NCNT—Receive Negative AU Pointer Justification Event

Counter (92–91H).................................................................................108

6.8.2.1 R_AU_PCNT—Receive Positive AU Pointer Justification Event

Counter (94–93H)....................................................................109

Receive HighOrder Path Termination Registers ...............................................109

6.9.1 R_HPT_C1—Receive HPT Configuration 1 Register (80H) ................109

6.9.2 R_HPT_C2—Receive HPT Configuration 2 Register (81H) ................110

6.9.3 J1_RSTR_C—J1 Expected String Control Register (8AH) ..................111

6.9.4 J1_RSTR_D—J1 Expected String Data Register (8BH) ......................111

6.9.5 EXP_C2—Expected C2 byte Register (82H) .......................................111

6.9.6 R_C2—Received C2 byte Register (83H)............................................111

6.9.7 R_K3—Received K3 byte Register (84H) ............................................111

6.9.8 R_HPT_RDI—Received HPT RDI Bits Register (85H) ........................112

6.9.9 B3_ECNT—B3 Error Event Counter (87–86H) ....................................112

6.9.10 HPTREI_CNT—HPT REI Counter (89–88H) .......................................112

Transmit Regenerator and Multiplexer Section Termination Registers.............113

Datasheet

LXT6051 Related Products

	LXT6051
Description	Terminator, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208
Maker	Cortina Systems Inc
Objectid	1809646163
Parts packaging code	QFP
package instruction	FQFP,
Contacts	208
Reach Compliance Code	compliant
compound_id	6912915
JESD-30 code	S-PQFP-G208
length	28 mm
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	4.1 mm
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ATM/SONET/SDH TERMINATOR
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

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