PROCESS
Small Signal Transistor
CP221
Central
TM
NPN- High Voltage Darlington Transistor Chip
Semiconductor Corp.
PROCESS DETAILS
Process
Die Size
Die Thickness
Base Bonding Pad Area
Emitter Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
GROSS DIE PER 4 INCH WAFER
7,290
PRINCIPAL DEVICE TYPES
CZT2000
EPITAXIAL BASE
39.5 X 39.5 MILS
9.8 MILS
3.9 x 5.1 MILS
7.9 x 3.9 MILS
Al - 24,000Å
Au - 12,000Å
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R1 (1-August 2002)