TFRA28J133BAL-1-DB datasheet, PDF

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TFRA28J133BAL-1-DB: DescriptionFramer, PBGA456, PLASTIC, BGA-456; CategoryWireless rf/communication Telecom circuit; File Size1MB，48 Pages; ManufacturerBroadcom

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TFRA28J133BAL-1-DB Overview

Framer, PBGA456, PLASTIC, BGA-456

TFRA28J133BAL-1-DB Parametric

Parameter Name	Attribute value
Maker	Broadcom
package instruction	BGA,
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B456
JESD-609 code	e0
length	35 mm
Number of functions	1
Number of terminals	456
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.54 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	35 mm

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Hardware Design Guide

October 24, 2003

TFRA28J13 Superframer

DS3/DS2/DS1/E1/DS0

1 Introduction

The documentation package for the TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system chip consists of the following

documents:

The

Supermapper Family Register Description

and the

Supermapper Family System Design Guide.

These two docu-

ments are available on a password-protected website.

The

Superframer Product Description,

and the

Superframer Hardware Design Guide

(this document). These two docu-

ments are available on the public website shown below.

If the reader displays this document using

Acrobat Reader

, clicking on any blue text will bring the reader to that reference

point. Clicking on the back arrow (Go to previous View) in the toolbar of the

Acrobat Reader

will bring the reader back to the

starting point.

To access related documents, including the documents mentioned above, please go to the following public website, or con-

tact your Agere representative (see the last page of this document).

http://www.agere.com/enterprise_metro_access/mappers_muxes.html

This document describes the hardware interfaces to the Agere Systems Inc. TFRA28J13 Superframer device. Information

relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing

diagrams, ac timing parameters, packaging, and operating conditions are included.

DS2

AIS Clk

TCB & TDL

RCB & RDL

FRM

x28/x21

DS1/J1/E1

M13

Mux

PLL Interface

System Interfaces

(x1) DS3

DS1/J1/E1

DS2

DS3

148

Multifunction System I/O

Switching Modes:

PSB - x672 DS0/E0

CHI - x672 DS0/E0

Transport Modes:

TPG/TPM

MPU

Interface & Control

x28/x21

DS1/E1

DS1/J1/E1 (X29) - x28/x21 prot.

DS2 - x7 + prot.

NSMI Mode:

DS1/J1/E1 x28/x21

DJA

DS1 & E1

XClks

EHB 10/22/03 Superframer

MPU IF

Figure 1-1. Superframer Block Diagram and High-Level Interface Definition

TFRA28J13 Superframer

DS3/DS2/DS1/E1/DS0

Hardware Design Guide

October 24, 2003

Table of Contents

Contents

Page

1 Introduction ........................................................................................................................................................................1

2 Pin Information ...................................................................................................................................................................6

2.1 456-Pin PBGA Pin Diagram ........................................................................................................................................6

2.2 Pin Assignments for 456-Pin PBGA by Pin Number Order .........................................................................................7

2.3 Pin Assignments for 456-Pin PBGA by Signal Name ................................................................................................10

2.3.1 DS3 Port ...........................................................................................................................................................13

2.3.2 Framer PLL ......................................................................................................................................................19

2.3.3 Test Pins ..........................................................................................................................................................22

3 Pin Assignment Matrix .....................................................................................................................................................23

4 Electrical Characteristics .................................................................................................................................................26

4.1 Absolute Maximum Ratings .......................................................................................................................................26

4.2 Thermal Parameters (Definitions and Values) ...........................................................................................................26

4.3 Reliability ...................................................................................................................................................................27

4.4 Handling Precautions ................................................................................................................................................28

4.5 Operating Conditions .................................................................................................................................................28

4.5.1 Power Consumption .........................................................................................................................................28

4.6 Logic Interface Characteristics ..................................................................................................................................29

4.7 DS3 Timing ................................................................................................................................................................30

4.8 M13 Timing ................................................................................................................................................................31

4.9 Concentration Highway (CHI) Timing ........................................................................................................................32

4.10 Parallel System Bus Timing .....................................................................................................................................33

4.11 NSMI Timing (6-Pin) (to/from Framer) .....................................................................................................................34

4.12 NSMI Timing (7-Pin) (to/from Framer) .....................................................................................................................34

4.13 CHI Interface Timing ................................................................................................................................................35

4.14 PSB Interface Timing ...............................................................................................................................................36

4.15 Framer DS1/E1 Interface Timing .............................................................................................................................37

4.16 DJA DS1/E1 Interface Timing ..................................................................................................................................38

4.17 M13 DS1/E1 Interface Timing .................................................................................................................................39

4.18 Microprocessor Interface Timing .............................................................................................................................40

4.18.1 Synchronous Mode ........................................................................................................................................40

4.18.2 Asynchronous Mode ......................................................................................................................................42

4.19 General-Purpose Interface Timing ..........................................................................................................................45

5 Ordering Information ........................................................................................................................................................46

6 Outline Diagram ...............................................................................................................................................................47

6.1 456-Pin PBGA ...........................................................................................................................................................47

Agere Systems Inc.

Hardware Design Guide

October 24, 2003

TFRA28J13 Superframer

DS3/DS2/DS1/E1/DS0

Table of Contents

(continued)

Tables

Page

Table 2-1. Pin/Name...............................................................................................................................................................7

Table 2-2. Pin Assignments for 456-Pin PBGA by Signal Name..........................................................................................10

Table 2-3. DS3 Port..............................................................................................................................................................13

Table 2-4. DS3 Port C-Bit and Datalink Access ...................................................................................................................14

Table 2-5. M13 Multiplexer/Demultiplexer Receive Section .................................................................................................14

Table 2-6. Reference Clocks ................................................................................................................................................15

Table 2-7. Multifunction System Interface ............................................................................................................................16

Table 2-8. Framer PLL .........................................................................................................................................................19

Table 2-9. Microprocessor Interfaces ...................................................................................................................................20

Table 2-10. General-Purpose Interface ................................................................................................................................21

Table 2-11. Test Pins ...........................................................................................................................................................22

Table 2-12. Analog Power and Ground Signals ...................................................................................................................22

Table 3-1. Pin Matrix ............................................................................................................................................................23

Table 4-1. Absolute Maximum Ratings.................................................................................................................................26

Table 4-2. Thermal Parameter Values .................................................................................................................................27

Table 4-3. Reliability Data ....................................................................................................................................................27

Table 4-4. Handling Precaution ............................................................................................................................................28

Table 4-5. Recommended Operating Conditions .................................................................................................................28

Table 4-6. Power Consumption ............................................................................................................................................28

Table 4-7. Logic Interface Characteristics ............................................................................................................................29

Table 4-8. DS3 Input Clock Specifications ...........................................................................................................................30

Table 4-9. Input Timing Specifications .................................................................................................................................30

Table 4-10. Output Timing Specifications.............................................................................................................................30

Table 4-11. M13 Clock Specifications ..................................................................................................................................31

Table 4-12. Input Timing Specifications ...............................................................................................................................31

Table 4-13. Output Timing Specifications.............................................................................................................................31

Table 4-14. CHI Transmit Timing Characteristics.................................................................................................................32

Table 4-15. CHI Receive Timing Characteristics..................................................................................................................32

Table 4-16. PSB Interface Transmit Timing Characteristics.................................................................................................33

Table 4-17. PSB Interface Receive Timing Characteristics..................................................................................................33

Table 4-18. NSMI Input/Output Clock Specifications ...........................................................................................................34

Table 4-19. Input Timing Specifications ...............................................................................................................................34

Table 4-20. Output Timing Specifications.............................................................................................................................34

Table 4-21. NSMI Output Clock Specifications ....................................................................................................................34

Table 4-22. NSMI Input Timing Specifications .....................................................................................................................35

Table 4-23. NSMI Output Timing Specifications...................................................................................................................35

Table 4-24. CHI Interface Clock Specifications ....................................................................................................................35

Table 4-25. CHI Interface Input Timing Specifications .........................................................................................................35

Table 4-26. CHI Interface Output Timing Specifications ......................................................................................................35

Table 4-27. PSB Interface Clock Specifications ...................................................................................................................36

Table 4-28. PSB Interface Input Timing Specifications ........................................................................................................36

Table 4-29. PSB Interface Output Timing Specifications .....................................................................................................36

Table 4-30. Framer DS1/E1 Interface Clock Specifications .................................................................................................37

Table 4-31. Framer DS1/E1 Interface Input Timing Specifications ......................................................................................37

Table 4-32. Framer DS1/E1 Interface Output Timing Specifications....................................................................................37

Table 4-33. DJA DS1/E1 Interface Clock Specifications .....................................................................................................38

Table 4-34. DJA DS1/E1 Interface Input Timing Specifications ...........................................................................................38

Table 4-35. DJA DS1/E1 Interface Output Timing Specifications ........................................................................................38

Table 4-36. M13 DS1/E1 Interface Clock Specifications .....................................................................................................39

Table 4-37. M13 DS1/E1 Interface Input Timing Specifications ...........................................................................................39

Table 4-38. M13 DS1/E1 Interface Output Timing Specifications ........................................................................................39

Agere Systems Inc.

TFRA28J133BAL-1-DB Related Products

	TFRA28J133BAL-1-DB
Description	Framer, PBGA456, PLASTIC, BGA-456
Maker	Broadcom
package instruction	BGA,
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B456
JESD-609 code	e0
length	35 mm
Number of functions	1
Number of terminals	456
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.54 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	35 mm

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