Standard Products
UT69R000 RadHard MicroController
Data Sheet
October 2005
Harvard architecture
- 64K data space
- 1M instruction space
High throughput engine
- 2 clocks per instruction
- 8 MIPS @ 16 MHz
- Static design
15 levels of interrupts
- 8 external user defined interrupts
- Machine error and power fail
Two on-board 16-bit interval timers
- Timer A, 10
µs/bit
- Timer B, 100
µs/bit
resolution
8-bit software controlled output discrete bus
Register- oriented architecture has 21
user-accessible registers
- 16-bit or 32-bit register configurations
Supports direct memory access (DMA) system
configuration
OSCOUT
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
NUI3
STATE1
DI1
DI2
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
OSCIN
SYSCLK
Built-in 9600 baud UART
Full military operating temperature range, -55
o
C to
+125
o
C, in accordance with MIL-PRF-38535 for Class Q
or V
Typical radiation performance:
- Total dose: 1.0E6 rads(Si)
- SEL Immune >100 MeV-cm
2
/mg
- LET
TH
(0.25) = 60 MeV-cm
2
/mg
- Saturated Cross Section (cm
2
) per bit, 1.2E-7
- 2.3E-11 errors/bit-day, Adams to 90%
geosynchronous heavy ion
Post-radiation AC/DC performance characteristics
guaranteed by MIL-STD-883 Method 1019 testing
at 1.0E6 rads(Si)
Latchup immune 1.5-micron CMOS, epitaxial,
double-level-metal technology
Packaging options:
- 132-lead flatpack
- 144-pin pingrid array (plus one index pin)
16
TIMCLK
TES
T
UARTOUT
UARTIN
UART
OSCILLATOR
/CLOCK
SHIFT REG
PROCESSOR
CONTROL
LOGIC
ID
32
GENERAL
PURPOSE
REGISTERS
TBR
RBR
TR
32
32
BIT REG
32
TB
IM
TEMP DEST
16
TEMP SRC
FR
PI
ST
SW
32
32
16
16
16
16
16
16
16
I/O
MUX
INSTRUCTION
DATA
16
IC/ICs
INSTRUCTION
ADDRESS
MCHNE1
BTERR
MCHNE2
MPROT
PFAIL
INT5
INT6
INT0-4
MRST
20
ADD
MUX
32
ACC
32
PIPELINE
BUS
CONTROL
8
16
OD(7:0)
OPERAND
DATA
DTACK
M/IO
R/WR
DS
OPERAND
ADDRESS
A MUX
INTER-
RUPTS
B MUX
32-BIT ALU
16
32
16
ADDR
MUX
5
Figure 1. UT69R000 Functional Block Diagram
Table of Contents
1.0
Introduction ..................................................................................................................... 4
1.1 General Description .............................................................................................. 4
1.2 General Operation ................................................................................................. 4
Register File .................................................................................................................... 6
2.1 General Purpose Registers .................................................................................... 6
2.2 Specialized Registers ............................................................................................ 6
2.2.1 Specialized Register Description ................................................................. 6
Instruction Port.............................................................................................................. 16
3.1 Instruction Port Operations ................................................................................. 17
3.1.1 STRI Instruction Bus Cycle ....................................................................... 17
3.1.2 LRI Instruction Bus Cycle ......................................................................... 18
Operand Port ................................................................................................................. 19
4.1 Operand Bus Cycle Operation ............................................................................ 20
4.2 DMA Operation and Bus Arbitration.................................................................. 23
Discrete Input/Output.................................................................................................... 25
5.1 Output Discrete Bus ............................................................................................ 25
5.2 Discrete Inputs .................................................................................................... 26
Interrupts ....................................................................................................................... 26
6.1 Interrupt Control ................................................................................................. 26
6.1.1 Interrupt Status........................................................................................... 27
6.1.2 Interrupt Processing and Vectoring ............................................................ 27
6.2 Interrupt Sources ................................................................................................. 28
6.3 Interrupt Hardware.............................................................................................. 28
6.4 Interrupt Latency................................................................................................. 28
Monitor ......................................................................................................................... 28
7.1 Using the Monitor ............................................................................................... 29
7.1.1 Examine Command.................................................................................... 33
7.1.2 Modify Command ...................................................................................... 33
7.1.3 Continue Command ................................................................................... 34
7.1.4 Run Command ........................................................................................... 34
Internal UART Operation.............................................................................................. 34
8.1 UART Transmitter Operation ............................................................................. 34
8.2 UART Receiver Operation.................................................................................. 35
Programming Interface.................................................................................................. 35
9.1 Data Formats ....................................................................................................... 35
9.2 Instruction Formats ............................................................................................. 36
9.3 Addressing Modes............................................................................................... 37
9.4 Data Movement Operations ................................................................................ 38
Pin Description.............................................................................................................. 39
Absolute Maximum....................................................................................................... 46
Recommended Operating Conditions ........................................................................... 46
DC Electrical Characteristics ........................................................................................ 47
AC Electrical Characteristics ........................................................................................ 48
Packaging ...................................................................................................................... 58
Ordering ........................................................................................................................ 60
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
2
RD0 - RD15
RA19
RA18
RA17
RA16
RA15
RA14
RA13
RA12
RA11
RA10
RA9
RA8
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
NUI1
NUI2
NUI3
DI1
DI2
STATE1
OSCIN
OSCOUT
UARTIN
UARTOUT
TIMCLK
TEST
INSTRUCTION DATA PORT
BUS
ARBITRATION
BRQ
BGNT
BUSY
BGACK
BUS
CONTROL
UT69R000
INSTRUCTION
ADDRESS
BUS
CLOCK
DTACK
M/ IO
R/ WR
DS
SYSCLK
OD0
OD1
OD2
OD3
OUTPUT
DISCRETES
PROCESSOR
STATUS
OD4
OD5
OD6
OD7
OSCILLATOR
OE
WE
MEMORY
UART
MCHNE1
BTERR
MCHNE2
MPROT
NUI4
INT4
INT3
INT2
INT1
INT0
PFAIL
INT5
INT6
MRST
INTERRUPTS/
EXCEPTIONS
OPERAND
ADDRESS
BUS
OPERAND
DATA BUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0 - D15
Figure 2. UT69R000 Pin Function Diagram
3
1.0 Introduction
The UT69R000 is a radiation-hardened high-performance
microcontroller designed, manufactured, and tested to meet
rigorous radiation environments. UTMC designed and
implemented the UT69R000 using an advanced radiation-
hardened twin-well CMOS process. The combination of
radiation-hardness, high throughput, and low power
consumption makes the UT69R000 ideal for high-speed
systems in satellites, missiles, and avionics applications.
1.1 General Description
The UT69R000 is a versatile microcontroller designed to meet
real-time control type applications. Support functions often
found external to a microprocessor are integrated within the
microcontroller. Functions include UART, interval timers, 10
external interrupt vectors, and a 8-bit output discrete bus.
The UT69R000 core (machine) is a two port microcontroller
that accesses instructions from a 1M x 16 instruction port; a
second port (64K x 16 data port) is available for data storage.
Data transfer acknowledge allows the addition of wait states
on the data port. The machine performs overlapping fetches
and executes speeding instruction throughput. A 12 MHz
operating clock frequency provides up to 6 MIPS of
throughput. A later section of this data sheet expands on this
concept.
The UT69R000 architecture is based on 20 16-bit general
purpose registers providing, the programmer with extensive
register support. The UT69R000’s flexibility is enhanced by
the concatenation of 16-bit registers into 32-bit registers. In
addition, all registers are available for use as either the source
or destination for any register operation.
All UT69R000 circuitry is of static design. Internal registers,
counters, and latches do not require refresh as with dynamic
circuit design. Therefore the UT69R000 can operate from DC
to the upper frequency limit of 16 MHz. This type of operation
is especially useful in power critical applications such as
satellites.
The UT69R000 fully supports multiprocessor systems, DMA,
and complex bus arbitration. Bus control passes among bus
masters operating on the same bus. The bus master can be one
of several UT69R000s or any other device requiring DMA.
The UT69R000 supports 15 levels of vectored interrupts. Ten
of these are external interrupts, all of which are user-definable.
All interrupts are serviced in order of priority.
The UT69R000’s three basic instruction formats support 16-
bit and 32-bit instruction. The formats are Register-to-Register,
Register-to-Literal, and Register-to-Long-Immediate
instructions.
Figure 3 shows the UT69R000’s general system architecture.
1.2 General Operation
The UT69R000 reduced instruction set consists of 35 separate
instructions. Most of these instructions execute in two clock
cycles providing high-throughput. The UT69R000 has a
Harvard architecture which incorporates two address and two
data buses. One set of address and data buses interface with
instruction memory (instruction port) and the other interfaces
with data memory (data port). The instruction port consists of
a 20-bit address bus and 16-bit data bus. The maximum
program length of any program is 1 mega-word. The data port
consists of a 16-bit address and data bus, allowing access to
64K x 16 of data storage.
The instruction port is dedicated to the storage of instruction
code; however , two instructions exist that allow the instruction
port manipulation by the machine. These instructions are the
Load Register from Instruction Memory (LRI) and Store
Register to Instruction Memory (STRI).
INSTRUCTION
DATA
16
INSTRUCTION
MEMORY
20
INSTRUCTION
ADDRESS
UT69R000
DATA
16
CONTROL
ADDRESS
16
DATA
MEMORY
Figure 3. UT69R000 General System Architecture
4
The UT69R000 begins operation by first generating an address
on the instruction port; valid data (instruction) is then latched
into the Primary Instruction Register (PIR). After the machine
stores the instruction in the PIR, the machine begins execution
of the instruction in the Instruction Register (IR). If the present
instruction in the IR requires only internal processing, the
machine does not exercise the data bus. If the machine needs
additional data to complete the instruction the machine begins
arbitration for the data port.
Data port arbitration begins with the machine asserting the Bus
Request (BRQ) signal. The machine samples the Bus Grant
(BGNT) and Bus Busy (BUSY) signals on the falling edge of
the clock (OSCIN). When the machine detects that the previous
bus controller has relinquished control of the bus, the machine
generates a Bus Grant Acknowledge (BGACK) signal
signifying that it has taken control of the bus (i.e., data port).
After the UT69R000 takes control of the bus, it generates valid
address and data information. If the machine is interfacing to
slow memory or other peripheral devices that require long
memory-access times, the Data Transfer Acknowledge
(DTACK) signal extends the memory cycle time. By holding
off the assertion of DTACK, the slow device lengthens the
memory cycle until it can provide data for the machine.
The UT69R000 controls the vectoring and prioritizing of
interrupt service. Internal logic selects one of 15 interrupt
vectors, each interrupt vector is allocated four memory
locations. Use the four memory locations to store return from
interrupt service address information along with the interrupt
service routine’s location. The UT69R000 controls prioritizing
of coincident interrupts.
Perform UART control and maintenance via input/output
commands OTR and INR. These commands allow the
programmer to read UART status, and error information, as
well as upload and download information to the receive and
transmit buffers respectively.
Figure 4 shows an example of a system configuration.
4
INSTRUCTION MEMORY
CAN ONLY BE ACCESSED
BY THE UT69R000
BRQ
BGNT
BUSY
BGACK
16
BUS
ARBITER
DMA
DEVICE
#1
1553
I/F
DMA
DEVICE
#2
INSTRUCTION
MEMORY
1M X 16
(MAX)
INSTRUCTION
DATA
INSTRUCTION
ADD
OP ADD
OE
OP DATA
WE CONTROL
16
16
6
20
INTERNALLY
PULLED LOW
USER-
DEFINED
SYSTEM
INTERRUPTS
8
NUI3
GENERAL
PURPOSE
MEMORY
I/O
DEVICE #1
I/O
DEVICE #2
UT69R000
UART
I/F
X
C
V
R
SERIAL I/O
Figure 4. The UT69R000 Example System Configuration
5
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