a
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
LC MOS
(8+4) Loading Dual 12-Bit DAC
AD7537
FUNCTIONAL BLOCK DIAGRAM
2
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1,
CS, WR
and
UPD.
Data is
loaded to the input registers when
CS
and
WR
are low. To
transfer this data to the DAC registers,
UPD
must be taken low
with
WR.
Added features on the AD7537 include an asynchronous
CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC
2
MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V V
DD
, with
±
10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7537–SPECIFICATIONS
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature Coefficient
2
;
∆Gain/∆Temperature
Output Leakage Current
I
OUTA
+25°C
T
MIN
to T
MAX
I
OUTB
+25°C
T
MIN
to T
MAX
REFERENCE INPUT
Input Resistance
V
REFA
, V
REFB
Input Resistance Match
DIGITAL INPUTS
V
IH
(lnput High Voltage)
V
IIL
(Input Low Voltage)
I
IN
(Input Current)
+25°C
T
MIN
to T
MAX
C
IN
(lnput Capacitance)
2
POWER SUPPLY
3
V
DD
I
DD
J, A
Versions
12
±
1
±
1
±
6
K, B
Versions
12
±
1/2
±
1
±
3
(V
DD
= +12 V to +15 V, 10%, V
REFA
= V
REFB
= 10 V; I
OUTA
= AGND = 0 V,
I
OUTB
= AGNDB = 0 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
L, C
Versions
12
±
1/2
±
1
±
1
S
Version
12
±
1
±
1
±
6
T
Version
12
±
1/2
±
1
±
3
U
Version
12
±
1/2
±
1
±
2
Units
Bits
LSB max
LSB max
LSB max
Test Conditions/Comments
All grades guaranteed mono-
tonic over temperature.
Measured using R
FBA
, R
FBB
.
Both DAC registers loaded
with all 1s.
±
5
10
150
10
150
9
20
±
3
2.4
0.8
±
1
±
10
10
10.8/16.5
2
±
5
10
150
10
150
9
20
±
3
2.4
0.8
±
1
±
10
10
10.8/16.5
2
±
5
10
150
10
150
9
20
±
1
2.4
0.8
±
1
±
10
10
10.8/16.5
2
±
5
10
250
10
250
9
20
±
3
2.4
0.8
±
1
±
10
10
10.8/16.5
2
±
5
10
250
10
250
9
20
±
3
2.4
0.8
±
1
±
10
10
10.8/16.5
2
±
5
10
250
10
250
9
20
±
1
2.4
0.8
±
1
±
10
10
10.8/16.5
2
ppm/°C max Typical value is 1 ppm/°C
nA max
nA max
nA max
nA max
kΩ min
kΩ max
% max
V min
V max
µA
max
µA
max
pF max
V min/V max
mA max
V
IN
= V
DD
DAC A Register loaded
with all 0s
DAC B Register loaded
with all 0s
Typical Input Resistance = 14 kΩ
Typically
±
0.5%
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(V
DD
= +12 V to +15 V; V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
Parameter
Output Current Settling Time
T
A
= +25 C
1.5
T
A
= T
MIN
, T
MAX
Units
µs
max
Test Conditions/Comments
To 0.01% of full-scale range. I
OUT
load = 100
Ω,
C
EXT
= 13 pF.
DAC output measured from falling edge of
WR.
Typical Value of Settling Time is 0.8
µs.
Measured with V
REFA
= V
REFB
= 0 V. I
OUTA
, I
OUTB
load = 100
Ω,
C
EXT
= 13 pF. DAC registers alternately loaded with all 0s and all 1s.
V
REFA
, V
REFB
= 20 V p-p 10 kHz sine wave.
DAC registers loaded with all 0s.
Digital-to-Analog Glitch lmpulse
AC Feedthrough
4
V
REFA
to I
OUTA
V
REFB
to I
OUTB
Power Supply Rejection
∆Gain/∆V
DD
Output Capacitance
C
OUTA
C
OUTB
C
OUTA
C
OUTB
Channel-to-Channel Isolation
V
REFA
to I
OUTB
V
REFB
to I
OUTA
Digital Crosstalk
Output Noise Voltage Density
(10 Hz–100 kHz)
Total Harmonic Distortion
NOTES
1
Temperature range as follows:
7
nV-s typ
–70
–70
±
0.01
70
70
140
140
–84
–84
7
25
–82
–65
–65
±
0.02
70
70
140
140
dB max
dB max
% per % max
∆V
DD
= V
DD
max – V
DD
min
pF max
pF max
pF max
pF max
dB typ
dB typ
nV-s typ
nV/√Hz typ
dB typ
2
3
DAC A, DAC B loaded with all 0s
DAC A, DAC B loaded with all 1s
V
REFA
= 20 V p-p 10 kHz sine wave, V
REFB
= 0 V.
Both DACs loaded with all 1s.
V
REFB
= 20 V p-p 10 kHz sine wave, V
REFA
= 0 V.
Both DACs loaded with all 1s.
Measured for a Code Transition of all 0s to all 1s.
I
OUTA
, I
OUTB
load = 100
Ω,
C
EXT
= 13 pF.
Measured between R
FBA
and I
OUTA
or R
FBB
and I
OUTB.
Frequency of measurement is 10 Hz–100 kHz.
V
IN
= 6 V rms, 1 kHz. Both DACs loaded with all 1s.
J, K, L Versions: –40°C to +85°C;
A, B, C Versions: –40°C to +85°C;
S, T, U Versions: –55°C to +125°C
Specifications subject to change without notice.
Sample tested at +25°C to ensure compliance.
Functional at V
DD
= 5 V, with degraded specifications.
4
Pin 12 (DGND) on ceramic DIPs is connected to lid.
–2–
REV. 0
AD7537
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Limit at
T
A
= +25 C
15
15
60
25
0
0
80
80
(V
DD
= +10.8 V to +16.5 V, V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V.)
Limit at
T
A
= +55 C
to +125 C
30
25
80
25
0
0
100
100
Limit at
T
A
= –40 C
to +85 C
15
15
80
25
0
0
80
80
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
Chip Select or Update to Write Setup Time
Chip Select or Update to Write Hold Time
Write Pulse Width
Clear Pulse Width
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise stated)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
REFA
, V
REFB
to AGNDA, AGNDB . . . . . . . . . . . . . . . .
±
25 V
V
RFBA
, V
RFBB
to AGNDA, AGNDB . . . . . . . . . . . . . . . .
±
25 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
I
OUTA
, I
OUTB
to DGND . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, V
DD
+0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C
Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C
Extended Hermetic (S, T, U Versions) . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
1
Model
2
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Relative Gain
Accuracy Error
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
6 LSB
±
3 LSB
±
1 LSB
±
6 LSB
±
3 LSB
±
1 LSB
±
6 LSB
±
3 LSB
±
1 LSB
±
6 LSB
±
3 LSB
±
2 LSB
±
6 LSB
±
3 LSB
±
2 LSB
Package
Option
3
N-24
N-24
N-24
P-28A
P-28A
P-28A
Q-24
Q-24
Q-24
Q-24
Q-24
Q-24
E-28A
E-28A
E-28A
Figure 1. Timing Diagram
AD7537JN
AD7537KN
AD7537LN
AD7537JP
AD7537KP
AD7537LP
AD7537AQ
AD7537BQ
AD7537CQ
AD7537SQ
AD7537TQ
AD7537UQ
AD7537SE
AD7537TE
AD7537UE
NOTES
1
Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of
cerdip packages (Q-24).
2
To order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
REV. 0
–3–
AD7537
PIN FUNCTION DESCRIPTION (DIP)
PIN
1
2
3
4
5
6–14
12
15
16
17
18
19
20
21
22
23
24
MNEMONIC
AGNDA
I
OUTA
R
FBA
V
REFA
CS
DB0–DB7
DGND
A0
A1
CLR
WR
UPD
V
DD
V
REFB
R
FBB
I
OUTB
AGNDB
DESCRIPTION
Analog Ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip Select Input Active low.
Eight data inputs, DB0–DB7.
Digital Ground.
Address Line 0.
Address Line 1.
Clear Input. Active low. Clears all
registers.
Write Input. Active low.
Updates DAC Registers from inputs
registers.
Power supply input. Nominally +12 V
to +15 V, with
±
10% tolerance.
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog Ground for DAC B.
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor R
FBA
is used with an op amp
(see Figures 4 and 5) to convert the current flowing in I
OUTA
to
a voltage output.
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
C
OUT
is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
The current source I
LKG
is composed of surface and junction
leakages and approximately doubles every 10°C. R
0
is the
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATION
PIN CONFIGURATIONS
DIP
LCCC
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7537 Truth Table
CLR UPD CS WR
A1 A0 FUNCTION
1
1
0
1
PLCC
1
1
X
1
1
1
1
0
1
X
X
0
0
0
0
1
X
1
X
0
0
0
0
0
X
X
X
0
0
1
1
X
X
X
X
0
1
0
1
X
1
1
1
1
1
0
0
0
X
X
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
DAC A, DAC B Registers are
Transparent
NOTES: X = Don’t care
CIRCUIT INFORMATION – D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between I
OUTA
and AGNDA. The
–4–
Figure 3. Equivalent Analog Circuit for DAC A
REV. 0
Applications–AD7537
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that V
OUTA
or
V
OUTB
is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
V
OUTA
(V
OUTB
) = –V
IN
(4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that V
OUTA
(V
OUTB
) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for V
OUTA
(V
OUTB
) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of V
IN
or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register
MSB
LSB
Analog Output,
V
OUTA
or V
OUTB
2047
+V
IN
2048
1
+V
IN
2048
1111 1111 1111
Binary Number in
DAC Register
MSB
LSB
Analog Output,
V
OUTA
or V
OUTB
1000 0000 0001
1000 0000 0000
0111 1111 1111
1111 1111 1111
4095
−V
IN
4096
2048
−V
IN
= −
12
V
IN
4096
1
−V
IN
4096
0
V
–5–
0
V
1
−V
IN
2048
2048
−V
IN
= −V
IN
2048
1000 0000 0000
0000 0000 0000
0000 0000 0001
0000 0000 0000
REV. 0
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