12061A6R8JAT1A datasheet, PDF - EEWORLD Datasheet

12061A6R8JAT1A: DescriptionCeramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0000068uF, Surface Mount, 1206, CHIP; CategoryPassive components capacitor; File Size792KB，4 Pages; ManufacturerAVX; Environmental Compliance

Download Datasheet Parametric View All

12061A6R8JAT1A Overview

Ceramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0000068uF, Surface Mount, 1206, CHIP

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	AVX
package instruction	, 1206
Reach Compliance Code	compliant
ECCN code	EAR99
capacitance	0.0000068 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
JESD-609 code	e3
Manufacturer's serial number	1206
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	5%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
method of packing	TR, EMBOSSED, 7 INCH
positive tolerance	5%
Rated (DC) voltage (URdc)	100 V
size code	1206
surface mount	YES
Temperature characteristic code	C0G
Temperature Coefficient	-/+30ppm/Cel ppm/°C
Terminal surface	Matte Tin (Sn) - with Nickel (Ni) barrier
Terminal shape	WRAPAROUND

EEWORLD University ---- Proteus from entry to mastery: Proteus from entry to mastery : https://training.eeworld.com.cn/course/4551Proteus not only has the simulation functions of other EDA tool software, but also can simulate single-chip microcomputers an...; 老白菜 Embedded System

C6000 DSP code online compilation problem: The performance of ARM processors is increasing day by day, and in many application systems, there are ARM+DSP solutions. This article proposes a new idea to use ARM to compile DSP code online, downlo...; Jacktang DSP and ARM Processors

EEWORLD University ---- Webinar: Thermal Monitoring and Protection: Webinar: Thermal Monitoring and Protection : https://training.eeworld.com.cn/course/5285Thermal monitoring is a classic techniques used to enhance system efficiency while ensuring system safety and he...; hi5 Talking

Understanding of multi-core DSP C6678 shared memory issues: [size=4] MSMC is configured as L2 by default, and can be configured as L3 according to user needs. Since configuring it as L3 only does address mapping, the physical access time should still be of the...; fish001 DSP and ARM Processors

Help with Renesas chips: What can be used to read and write the Renesas R7F7010573 chip?...; z361672505 Renesas Electronics MCUs

Redesigned 3D printer to print and test preliminary coating: First, here is a picture of what I have done so far for the sake of indexing. . .[b][color=#5E7384]This content was originally created by [size=3]cardin6[/size], a user of EEWORLD forum. If you want t...; cardin6 Creative Market

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components