Quad Port PHY (Physical Layer)
for 25.6, 51.2, and 204.8 Mbps
ATM Networks and Backplane
Applications
IDT77V1264L200
Features List
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Commercial and Industrial Temperature Ranges
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Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
four 204.8 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Operates at 25.6, 51.2, 102.4, 204.8 Mbps data rates
Individual Selection of Port Data Rates
Backwards Compatible with 77V1254L25
UTOPIA Level 1 or UTOPIA Level 2
3-Cell Transmit and Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Description
The IDT77V1264L200 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1264L200 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1264L200 also operates at 51.2 Mbps and 204.8 Mbps, and is
well suited to backplane driving applications.
The 77V1264L200-ATM layer interface is selectable as either: 16-bit
UTOPIA Level 2 or 8-bit UTOPIA Level 1 Multi-PHY.
The IDT77V1264L200 is fabricated using IDT's state-of-the-art
CMOS technology, providing the highest levels of integration, perfor-
mance and reliability, with the low-power consumption characteristics of
CMOS.
Block Diagram
TXREF
TXCLK
TXDATA[15:0]
TXPARITY
TXSOC
TXEN
TXCLAV
TXADDR[4:0]
MODE[1:0]
PHY-ATM
Interface
(UTOPIA or DPI)
(UTOPIA)
Driver
P/S and S/P
NRZI
Clock Recovery
+
Tx 1
-
+
Rx 1
-
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Driver
P/S and S/P
NRZI
Clock Recovery
+
TX 0
-
+
RX 0
-
RXADDR[4:0]
RXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXEN
RXCLAV
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
INT
RST
Microprocessor
Interface
RD
WR
CS
AD[7:0]
ALE
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Driver
P/S and S/P
NRZI
Clock Recovery
+
- TX 2
+
- RX 2
TX/RX ATM
Cell FIFO
OSC
Scrambler/
Descrambler
4
4
5B/4B
Encoding/
Decoding
Driver
P/S and S/P
NRZI
Clock Recovery
+
- TX 3
+
- RX 3
RXREF
RXLED[3:0]
TXLED[3:0]
3505 drw 01
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
September 20, 2001
DSC 6029
IDT77V1264L200
Applications
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Up to 204.8Mbps backplane transmission
Rack-to-rack short links
ATM Switches
77V1264L200 Overview
The 77V1264L200 is a four port implementation of the physical layer
standard for 25.6Mbps ATM network communications as defined by
ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical
layer is divided into a Physical Media Dependent sub layer (PMD) and
Transmission Convergence (TC) sub layer. The PMD sub layer includes
the functions for the transmitter, receiver and clock recovery for opera-
tion across 100 meters of category 3 and 5 unshielded twisted pair
(UTP) cable. This is referred to as the Line Side Interface. The TC sub
layer defines the line coding, scrambling, data framing and synchroniza-
tion.
On the other side, the 77V1264L200 interfaces to an ATM layer
device (such as a switch core or SAR). This cell level interface is config-
urable as either an 8-bit Utopia Level 1 Multi-PHY or 16-bit Utopia Level
2 interface, as determined by two MODE pins. This is referred to as the
PHY-ATM Interface. The pinout and front page block diagram are based
on the Utopia 2 configuration. Table 3 shows the corresponding pin func-
tions for the other two modes, and Figure 2 and Figure 3 show functional
block diagrams.
The 77V1264L200 is based on the 77105, and maintains significant
register compatibility with it. The 77V1264L200, however, has additional
register features, and also duplicates most of its registers to provide
significant independence between the four ports.
Access to these status and control registers is through the utility bus.
This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8kHz timing
marker, and provide LED indication of receive and transmit status.
Auto-Synchronization and Good Signal Indica-
tion
The 77V1264L200 features a new receiver synchronization algorithm
that allow it to achieve 4b/5b symbol framing on any valid data stream.
This is an improvement on earlier products which could frame only on
the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
ATM25 transceivers always transmit valid 4b/5b symbols, allowing
the 77V1264L200 receive section to achieve symbol framing and prop-
erly indicate receive signal status, even in the absence of ATM cells or
8kHz (X8) timing markers in the receive data stream. A state machine
monitors the received symbols and asserts the “Good Signal” status bit
when a valid signal is being received. “Good Signal” is deasserted and
the receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Operation at Speeds Above 25 Mbps
In addition to operation at the standard rate of 25.6 Mbps, the
77V1264L200 can be operated at a range of data rates, up to 204.8
Mbps, as shown in Table 3. For 204.8Mbps data rate applications,
ST6200T magnetics from Pulse Engineering can be used. These
magnetics have been tested to work over 10 meters of UTP 5 cable at
204.8Mbps. The rate is determined by the frequency of the OSC clock,
multiplied by the internal PLL clock multiplier factor (1x, 2x or 4x) as
determined in the Enhanced Control 2 Registers. Although the OSC
clock frequency is common to all ports of the PHY, the clock multiplier
factor can be set individually for each port. As an example, with a 64
MHz oscillator, this allows some ports to operate at 51.2 Mbps while
other ports are simultaneously operating at 204.8 Mbps.
When operating at clock multiples other than 1x, use of the RXREF
pin requires that the RXREF Pulse Width Select field in the LED Driver
and HEC Status/Control Registers be programmed to a value greater
than the default of 1 cycle.
Also, the PHY loopback mode without clock recovery (10) in the
Diagnostic Control Registers works only when the clock multiplier is 1x.
For higher multiples, the PHY loopback mode (01) with clock recovery
must be used.
Except as noted above, these higher speed configurations operate
exactly the same as the basic 25.6 Mbps configuration. The scrambling
and encoding are unchanged.
Table 1 shows some of the different data rates the PHY can operate
at with a 32MHz or 64MHz oscillator. Note that any oscillator frequency
between 32MHz and 64MHz can be used. For example, if a 48MHz
oscillator is used and the multiplier is set to 4x, the data rate would be
153.6Mbps.
Clock Multiplier
Control Bits
(Enhanced Control 2
Registers)
00 (1x)
01 (2x)
10 (4x)
64 MHz
00 (1x)
01 (2x)
10 (4x)
Reference
Clock (OSC)
32 MHz
Line Bit
Rate
(MHz)
32
64
128
64
128
256
Data
Rate
(Mbps)
25.6
51.2
102.4
51.2
102.4
204.8
Table 1 200 Speed Grade Option
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September 20, 2001
IDT77V1264L200
VDD
GND
TX0-
TX0+
VDD
MM
MODE1
MODE0
RXREF
TXREF
GND
TXLED3
TXLED2
TXLED1
TXLED0
VDD
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXEN
TXSOC
TXADDR4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TX1+
TX1-
GND
AGND
AVDD
RX0+
RX0-
AVDD
AGND
AGND
AVDD
RX1+
RX1-
AVDD
AGND
AGND
AVDD
AGND
OSC
AVDD
AGND
AGND
AVDD
RX2+
RX2-
AVDD
AGND
AGND
AVDD
RX3+
RX3-
AVDD
AGND
GND
TX2+
TX2-
77V1264L200
77V1254
144-PQFP
VDD
GND
TX3+
TX3-
VDD
DA
SE
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
VDD
ALE
CS
RD
WR
RST
GND
INT
VDD
GND
RXLED3
RXLED2
RXLED1
RXLED0
VDD
GND
RXDATA0
RXDATA1
RXDATA2
RXDATA3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
.
3505 drw 02
TXADDR3
VDD
TXADDR2
TXADDR1
TXADDR0
TXCLAV
TXCLK
GND
VDD
RXCLK
RXEN
RXADDR0
RXADDR1
GND
RXADDR2
RXADDR3
RXADDR4
RXCLAV
RXSOC
GND
VDD
RXPARITY
RXDATA15
RXDATA14
RXDATA13
RXDATA12
RXDATA11
RXDATA10
RXDATA9
RXDATA8
GND
VDD
RXDATA7
RXDATA6
RXDATA5
RXDATA4
Figure 1 Pin Assignments
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September 20, 2001
IDT77V1264L200
Signal Descriptions
Line Side Signals
Signal Name
RX0+,-
RX1+,-
RX2+,-
RX3+,-
TX0+,-
TX1+,-
TX2+,-
TX3+,-
Pin Number
139, 138
133, 132
121, 120
115, 114
4, 3
144, 143
110, 109
106, 105
I/O
In
In
In
In
Out
Out
Out
Out
Signal Description
Port 0 positive and negative receive differential input pair.
Port 1 positive and negative receive differential input pair.
Port 2 positive and negative receive differential input pair.
Port 3 positive and negative receive differential input pair.
Port 0 positive and negative transmit differential output pair.
Port 1 positive and negative transmit differential output pair.
Port 2 positive and negative transmit differential output pair.
Port 3 positive and negative transmit differential output pair.
Utility Bus Signals
Signal Name
AD[7:0]
ALE
CS
RD
WR
Pin Number
I/O
Signal Description
101, 100, 99, 98, 96, 95, 94, In/Out Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this
bus when a read is performed. Input data is sampled at the completion of a write operation.
93
91
90
89
88
In
In
In
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
edge of ALE. ALE must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain
asserted at all times if desired
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
deasserting WR and asserting RD and CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is
deasserted.
Miscellaneous Signals
Signal Name
DA
INT
Pin Number
103
85
I/O
In
Out
Signal Description
Reserved signal. This input must be connected to logic low.
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the
interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via
the interrupt Mask Registers.
Reserved signal. This input must be connected to logic low.
Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTO-
PIA Level 1. 10 and 11 are reserved.
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz or 64 MHz.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be per-
formed after power up prior to normal operation of the part.
Receive LED drivers. Driven low for 223 cycles of OSC, beginning with RXSOC when that port receives a
good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.
Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of
clock cycles when an x_8 command byte is received. Register 0x40 is programmed to indicate which port is
referenced. Note that when operating the 77V1264L200 at 2x or 4x multiple of OSC (See Enhanced Control
2 Registers) the RXREF pulse width (See LED Driver and HEC Status/Control Registers) must be pro-
grammed to any value greater than the default for proper operation of RXREF.
Table 2 Signal Descriptions (Part 1 of 3)
MM
MODE[1:0]
OSC
RST
RXLED[3:0]
RXREF
6
7, 8
126
87
82, 81, 80, 79
9
In
In
In
In
Out
Out
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September 20, 2001
IDT77V1264L200
SE
TXLED[3:0]
TXREF
102
12, 13, 14, 15
10
In
Out
In
Reserved signal. This input must be connected to logic low.
Ports 3 through 0 Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when this
port receives a cell for transmission. 8 mA drive current both high and low. One per port.
Transmit Reference. Synchronous to OSC. On the falling edge, an X_8 command byte is inserted into the
transmit data stream. Logic for this signal is programmed in register 0x40. Typical application is WAN timing.
Power Supply Signals
Signal Name
AGND
AVDD
GND
VDD
Pin Number
I/O
Signal Description
Analog ground. AGND supply a ground reference to the analog portion of the ship, which sources a more
constant current than the digital portion.
Analog power supply 3.3 ± 0.3V AVDD supply power to the analog portion of the chip, which draws a more
constant current than the digital portion.
Digital Ground.
Digital power supply. 3.3 ± 0.3V.
112, 117, 118, 123, 124,
____
127, 129, 130, 135, 136, 141
113, 116, 119, 122, 125,
128, 131, 134, 137, 140
____
2, 11, 44, 50, 56, 67, 77, 83, ____
86, 97, 107, 111, 142
1, 5, 16, 38, 45, 59, 68, 78,
84, 92, 104, 108
____
16-BIT UTOPIA 2 Signals (MODE[1:0] = 00)
Signal Name
RXADDR[4:0]
RXCLAV
Pin Number
53, 52, 51, 49, 48
54
I/O
In
Out
Signal Description
Utopia 2 Receive Address Bus. This bus is used in polling and selecting the receive port. The port addresses
are defined in bits [4:0] of the Enhanced Control Registers.
Utopia 2 Receive Cell Available. Indicates the cell available status of the addressed port. It is asserted when
a full cell is available for retrieval from the receive FIFO. When non of the four ports is addressed. RXCLAV is
high impedance.
Utopia 2 Receive Clock. This is a free running clock input.
Utopia 2 Receive Data. When one of the four ports is selected, the 77V1264L200 transfers received cells to
an ATM device across this bus. Also see RXPARITY.
Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus.
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
Utopia 2 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia 2 Transmit Address Bus. This bus is used in polling and selecting the transmit port. The port
addresses are defined in bits [4:0] of the Enhanced Control Registers.
Utopia 2 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the addressed port
for a full cell. When none of the four ports is addressed, TXCLAV is high impedance.
Utopia Transmit Clock. This is a free running clock input.
Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1264L200 for transmission.
Also see TXPARITY.
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA
bus.
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is checked and errors are indicated in
the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
Table 2 Signal Descriptions (Part 2 of 3)
RXCLK
46
In
Out
RXDATA[15:0] 59, 60, 31, 62, 63, 64, 65,
66, 69, 70, 71, 72, 73, 74,
75, 76
RXEN
RXPARITY
RXSOC
TXADDR[4:0]
TXCLAV
TXCLK
47
58
55
36, 37, 39, 40, 41
42
43
In
Out
Out
In
Out
In
In
TXDATA[15:0] 32, 31, 30, 29, 28, 27, 26,
25, 24, 23, 22, 21, 20, 19,
18, 17
TXEN
TXPARITY
34
33
In
In
TXSOC
35
In
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September 20, 2001
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