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UT54ACTS85-PVXH

Description
Magnitude Comparator, ACT Series, 4-Bit, True Output, CMOS, CDIP16, DIP-16
Categorylogic    logic   
File Size77KB,6 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

UT54ACTS85-PVXH Overview

Magnitude Comparator, ACT Series, 4-Bit, True Output, CMOS, CDIP16, DIP-16

UT54ACTS85-PVXH Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCobham PLC
package instructionDIP, DIP16,.3
Reach Compliance Codeunknown
Other featuresCASCADABLE
seriesACT
JESD-30 codeR-CDIP-T16
JESD-609 codee0
length19.05 mm
Logic integrated circuit typeMAGNITUDE COMPARATOR
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)22 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose1M Rad(Si) V
width7.62 mm
UT54ACS85/UT54ACTS85
Radiation-Hardened
4-Bit Comparators
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS85 and the UT54ACTS85 are 4-bit magnitude
comparators that perform comparison of straight binary and
straight BCD (8-4-2-1) codes. Three fully decoded decisions
about two 4-bit words (A, B) are made and are externally avail-
able at three outputs. Devices are fully expandable to any num-
ber of bits without external gates. The cascading paths of the
devices are implemented with only a two-gate-level delay to
reduce overall comparison times for long words. An alternate
method of cascading which further reduces the comparison time
is shown in the typical application data.
The devices are characterized over full military temperature
range of -55 C to +125 C.
LOGIC SYMBOL
A0
A1
A2
A3
(A<B)IN
(A=B)IN
(A>B)IN
B0
B1
B2
B3
(10)
(12)
(13)
(15)
(2)
(3)
(4)
(9)
(11)
(14)
(1)
3
<
=
>
0
B
A
<
=
>
(7)
(6)
(5)
(A<B)OUT
(A=B)OUT
(A>B)OUT
COMP
0
3
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
PINOUTS
16-Pin DIP
Top View
B3
(A<B)IN
(A=B)IN
(A>B)IN
(A>B)OUT
(A=B)OUT
(A<B)OUT
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A3
B2
A2
A1
B1
A0
B0
16-Lead Flatpack
Top View
B3
(A<B)IN
(A=B)IN
(A>B)IN
(A>B)OUT
(A=B)OUT
(A<B)OUT
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A3
B2
A2
A1
B1
A0
B0
51
RadHard MSI Logic

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