AS7C332MFT18A-65BC datasheet, PDF

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AS7C332MFT18A-65BC: DescriptionStandard SRAM, 2MX18, 6.5ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size566KB，23 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C332MFT18A-65BC Overview

Standard SRAM, 2MX18, 6.5ns, CMOS, PBGA165, BGA-165

AS7C332MFT18A-65BC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	6.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bit
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum standby current	0.1 A
Minimum standby current	3.14 V
Maximum slew rate	0.31 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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April 2004

AS7C332MFT18A

3.3V 2M

18 Flow-through synchronous SRAM

Features

•

Organization: 2,097152 words × 18 bits

Fast clock to data access: 6.5/7.5/8.5 ns

Fast OE access time: 3.5/3.5/4.0 ns

Fully synchronous flow-through operation

Asynchronous output enable control

Available in 100-pin TQFP package and 165-ball BGA

Individual byte write and global write

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Linear or interleaved burst control

•

Snooze mode for reduced power-standby

Common data inputs and data outputs

Boundary scan using IEEE 1149.1 JTAG function

NTD™

pipelined architecture available

(AS7C332MNTD18A, AS7C331MNTD32A/

AS7C331MNTD36A)

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All

trademarks mentioned in this document are the property of their

respective owners.

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[20:0]

CLK

CLR

Burst logic

Address

CLK

19 21

2M x 18

Memory

array

GWE

BWE

CE0

CE1

CE2

DQb

CLK

DQa

Byte Write

registers

Byte Write

CLK

registers

Enable

CLK

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

DQ[a,b]

Selection guide

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-65

7.5

6.5

310

140

110

-75

8.5

7.5

290

130

110

-85

8.5

270

130

110

Units

4/26/04, v 1.0

Alliance Semiconductor

1 of 23

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