Preliminary
GS8662T20/38AE-450/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future
144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaCIO DDR-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaCIO™ Family Overview
The GS8662T20/38AE are built in compliance with the
SigmaCIO DDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662T20/38AE SigmaCIO SRAMs are just
one element in a family of low power, low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662T20/38AE SigmaCIO DDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Common I/O x36 and x18 SigmaCIO DDR-II+ B2RAMs
always transfer data in two packets. When a new address is
loaded, A0 presets an internal 1 bit address counter. The
counter increments by 1 (toggles) for each beat of a burst of
two data transfer.
Common I/O x8 SigmaCIO DDR-II+ B2 RAMs always
transfer data in two packets. When a new address is loaded,
the LSB is internally set to 0 for the first read or write transfer,
and incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a x8 SigmaCIO DDR-
II+ B4 RAM is always one address pin less than the advertised
index depth (e.g., the 4M x 18 has a 2048K addressable index).
Parameter Synopsis
-450
tKHKH
tKHQV
2.22 ns
0.45 ns
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.3 ns
0.45 ns
-300
3.0 ns
0.45 ns
Rev: 1.00b 10/2009
1/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662T20/38AE-450/400/375/333/300
2M x 36 SigmaCIO DDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
MCL/SA
(144Mb)
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
BW1
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. MCL = Must Connect Low
Rev: 1.00b 10/2009
2/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662T20/38AE-450/400/375/333/300
4M x 18 SigmaCIO DDR-II SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
7
NC
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
11 x 15 Bump BGA—13 x 15 mm
2
Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. MCL = Must Connect Low
Rev: 1.00b 10/2009
3/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662T20/38AE-450/400/375/333/300
Pin Description Table
Symbol
SA
NC
R/W
BW0–BW3
LD
K
K
TMS
TDI
TCK
TDO
V
REF
ZQ
MCL
DQ
Doff
CQ
CQ
V
DD
V
DDQ
V
SS
QVLD
Description
Synchronous Address Inputs
No Connect
Synchronous Read/Write
Synchronous Byte Writes
Synchronous Load Pin
Input Clock
Input Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Data I/O
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Q Valid Output
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Input/Output
Input
Output
Output
Supply
Supply
Supply
Output
Comments
—
—
High: Read
Low: Write
Active Low
x18/x36 only
Active Low
Active High
Active Low
—
—
—
—
—
—
—
Three State
Active Low
—
—
1.8 V Nominal
1.5 V or 1.8 V Nominal
—
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V
DDQ
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K, or K cannot be set to V
REF
voltage.
Rev: 1.00b 10/2009
4/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662T20/38AE-450/400/375/333/300
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaCIO DDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is
possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaCIO DDR-II+ B2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.
SigmaCIO DDR-II+ B2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
Rev: 1.00b 10/2009
5/31
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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