64 Megabit FLASH EEPROM
DPZ4MX16NV3
DESCRIPTION:
The DPZ4MX16NV3 ‘’VERSA-STACK’’ module is a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers
(SLCC) mounted on a co-fired ceramic substrate. It offers 64
Megabits of FLASH EEPROM in a single package envelope of
1.090" x 1.090" x .400".
The DPZ4MX16NV3 is built with two stacks of 4 SLCC
packages each containing a 1 Meg x 8 FLASH memory
devices. Each SLCC is hermetically sealed making the
module suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers
a higher board density of memory than available with
conventional through-hole, surface mount, module or hybrid
techniques.
FEATURES:
•
Organizations: 4Meg x 16, 8 Meg x 8
•
Fast Access Times: 90, 100, 120, 150ns (max.)
•
High-Density Symmetrically
Blocked Architecture
- Sixteen 64 Kbyte Blocks Per Device
•
Extended Cycling Capability
- 10K Block Erase Cycles
•
Automated Byte Write and Block Erase
- Command User Interface
- Status Register
•
SRAM-Compatible Write Interface
•
Hardware Data Protection Feature
- Erase / Write Lockout during
Power Transitions
•
66 - Pin PGA ‘’VERSA-STACK’’ Package
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A19
I/O0 - I/O15
CE0 - CE7
WE
OE
V
PP
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Chip Enables
Write Enable
Output Enable
Programming
Voltage (+12.0V)
Power (+5V)
Ground
No Connect
PIN-OUT DIAGRAM
30A123-04
REV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPZ4MX16NV3
PRODUCT OVERVIEW
The DPZ4MX16NV3 is a high-performance 64 Megabit memory
organized as 8 -1 Mbyte (1,048,576 bytes) of 8 bits each. Sixteen
64 Kbyte (65,536 byte) blocks are included in each of the eight 1
Meg x 8 devices on the module. A memory map is shown in this
specification. A block erase operation erases one of the sixteen
blocks of memory in typically 1.6 seconds, independent of the
remaining blocks. Each block can be independently erased and
written 10,000 cycles. Erase Suspend mode allows system
software to suspend block erase to read data or execute code from
any other block of each device.
The Command User Interface serves as the interface between the
microprocessor or microcontroller and the internal operation of
the fuse devices.
Byte Write and Block Erase Automation allow byte write and
block erase operations to be executed using a two-write
command sequence to the Command User Interface. The
internal Write State Machine (WSM) automatically executes the
algorithms and timings necessary for byte write and block erase
operations, including verifications, thereby unburdening the
microprocessor or microcontroller. Writing of memory data is
performed in byte increments typically within 9µs, an 80%
improvement over current flash memory products.
The Status Register indicates the status of the WSM and when the
WSM successfully completes the desired byte write or block erase
operation.
Maximum access time is 150ns (t
ACC
) over the military
temperature range (-55
o
C to +125
o
C) and over V
DD
supply
Dense-Pac Microsystems, Inc.
again possible via the Read Array command. Erase
suspend/resume capability allows system software to suspend
block erase to read data and execute code from any other block.
COMMAND USER INTERFACE AND WRITE
AUTOMATION
An on-chip state machine controls block erase and byte write,
freeing the system processor for other tasks. After receiving the
Erase Setup and Erase Confirm commands, the state machine
controls block pre-conditioning and erase, returning progress via
the status Register. Byte write is similarly controlled, after
destination address and expected data are supplied. The program
and erase algorithms are regulated by the state machine, including
pulse repetition where required and internal verification and
margining of data.
DATA PROTECTION
Depending on the applica
tion, the system designer may
choose to make the V
PP
power supply switchable
(available
only when memory byte writes/block erases are required) or
hardwired to V
PPH
. When V
PP
= V
PPL
, memory contents
cannot be altered. The module Command User Interface
architecture provides protection from unwanted byte write or
block erase operations even when high voltage is applied to
V
PP
. Additionally, all functions are disabled whenever V
DD
is
below the write lockout voltage V
LKO
.
The module
accommodates either design practice and encourage
optimization of the processor-memory interface.
The two-step byte write/block erase Command User Interface
write sequence provides additional software write protection.
voltage range 4.5V to 5.5V.
When the CE pin is at V
DD
, the I
CC
CMOS Standby mode is
enabled.
PRINCIPLES OF OPERATION
MEMORY MAP *
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
* Per 1 Meg x 8 Device.
The device includes on-chip write automation to manage write
and erase functions. The Write State Machine allows for: 100%
TTL-level control inputs, fixed power supplies during block
erasure and byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up, or after return from deep
powerdown mode (see Table 1), the module functions as a
read-only memory. Manipulation of external memory-control
pins allow array read, standby and output disable operations.
Both Status Register and device identifier can also be accessed
through the Command User Interface when V
PP
= V
PPL
.
This same subset of operations is also available when high voltage
is applied to the V
PP
pin. In addition, high voltage on V
PP
enable successful block erasure and byte writing of the
device. All functions associated with altering memory
contents (byte write, block erase, status and device identifier)
are accessed via the Command User Interface and verified
through the Status Register.
Commands are written using standard microprocessor write
timings. Command User Interface contents serve as input to the
WSM, which controls the block erase and byte write circuitry.
Write cycles also internally latch addresses and data needed for
byte write or block erase operations. With the appropriate
command written to the register, standard microprocessor read
timings output array data, access the device identifier codes, or
output byte write and block erase status for verification.
Interface software to initiate and poll progress of internal byte
write and block erase can be stored in any of the module blocks.
This code is copied to, and executed from, system RAM during
actual flash memory update. After successful completion of byte
write and/or block erase, code/data reads from the module are
2
30A123-04
REV. D
Dense-Pac Microsystems, Inc.
DPZ4MX16NV3
BUS OPERATION
Flash memory reads, erases and writes in-system via the local
CPU. All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
DEVICE IDENTIFIER OPERATION
READ
The module has three read modes. The memory can be read from
any of its blocks, and information can be read from the device
identifier or Status Register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate read mode command to
the Command User Interface (array, device identifier, or Status
Register). The module automatically resets to Read Array mode
upon initial device powerup. The module has four control pins,
two of which must be logically active to obtain data at the outputs.
Chip Enable (
CE) is the device selection control, and when
The device identifier operation outputs the manufacturer code,
89H, and the device code, A2H, for each device. The system
CPU can then automatically match the device with its proper
block erase and byte write algorithms.
The manufacture and device codes are read via the Command
User Interface. Following a write of 90H to the Command User
Interface, a read from address location 00000H outputs the
manufacturer code (89H). A read from address location 00001H
outputs the device code (A2H). It is not necessary to have high
voltage applied to V
PP
to read the device identifier from the
Command User Interface.
WRITE
active enables the selected memory device. Output Enable
(OE) is the data input/output (I/O0 - I/O7, I/O8 - I/O15)
direction control, and when active derives data from the
selected memory onto the I/O bus. The AC Waveform for
Read Operations illustrates read bus cycle waveforms.
OUTPUT DISABLE
With OE at a logic-high level (V
IH
), the device outputs are
disabled. Output pins (I/O0 - I/O7, I/O8 - I/O15) are placed in a
high-impedance state.
the Command User Interface controls block erasure and byte
write. The contents of the interface register serve as input to
the internal write state machine.
Writes to the Command User Interface enable reading of device
data and device identifier. They also control inspection and
clearing of the Status Register. Additionally, when V
PP
= V
PPH
,
STANDBY
CE
at a logic-high level (V
IH
) places the module in standby
mode. Standby operation disables much of the modules
circuitry and substantially reduces device power
consumption. The outputs (I/O0 - I/O7, I/O8 - I/O15) are
placed in a high- impedance state independent of the status
of OE. If
each device is deselected during block erase or
The Command User Interface itself does not occupy an
addressable memory location. The interface register is a latch
used to store the command and address and data information
needed to execute the command. Erase Setup and Erase Confirm
commands require both appropriate command data and an
address within the block to be erased. The Byte Write Setup
command requires both appropriate command data and the
address of the location to be written.
The Command User Interface is written by bringing WE to a
logic-low level (V
IL
) while
CE is low. Addresses and data are
Refer to AC Write Characteristics and the AC Waveforms for Write
Operations, for specific timing parameters.
latched on the rising edge of WE. Standard microprocessor
write timing are used.
byte write, the device will continue functioning and
consuming normal active power until the operation
completes.
Table 1: BUS OPERATION
Mode
Read
1, 2
Output Disable
Standby
Device Identifier (Mfg.)
Device Identifier (Device)
Write
3, 4
CE
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
OE
V
IL
V
IH
X
V
IL
V
IL
V
IH
WE
V
IH
V
IH
X
V
IH
V
IH
V
IL
A0
X
X
X
V
IL
V
IH
X
V
PP
X
X
X
X
X
X
I/O0-I/O7,
I/O8-I/O15
D
OUT
HIGH-Z
HIGH-Z
89H
A2H
D
IN
NOTES:
1.
2.
3.
4.
Refer to DC Characteristics. When V
PP
= V
PPL
, memory contents can be read but not written or erased.
X can be V
IL
or V
IH
for control pins and addresses, and V
PPH
for V
PP
. See DC Characteristics for V
PPL
= V
PPL
voltages.
Command writes involving block erase or byte write are only successfully executed when V
PP
= V
PPH
.
Refer to Command Definitions for valid D
IN
during a write operation.
30A123-04
REV. D
3
DPZ4MX16NV3
COMMAND DEFINITIONS
When V
PPL
is applied to the V
PP
pin, read operations from the
Dense-Pac Microsystems, Inc.
Status Register, device identifier, or array blocks are enabled.
Placing V
PPH
on V
PP
enables successful byte write and block
erase operations as well.
Device operations are selected by writing specific commands into
the Command User Interface. Table 2 defines the device.
to the Command User Interface. The contents of the Status
Register are latched on the falling edge of OE or CE, whichever
occurs last in the read cycle. OE or
CE must be toggled to V
IH
before further reads to update the Status Register latch. The
Read Status Register command functions when V
PP
= V
PPL
or
V
PPH
.
CLEAR STATUS REGISTER COMMAND
READ ARRAY COMMAND
Upon initial device powerup the module defaults to Read Array
mode. This operation is also initiated by writing FFH into the
Command User Interface. Microprocessor read cycles retrieve
array data. The device remains enabled for reads until the
Command User Interface contents are altered. Once the internal
Write State Machine has started a block erase or byte write
operation, the device will not recognize the Read Array
command, until the WSM has completed it s operation. The Read
Array command is functional when V
PP
= V
PPL
or V
PPH
.
The Erase Status and Byte Write Status bits are set to “1”s by the
Write State Machine and can only be reset by the Clear Status
Register Command. These bits indicate various failure conditions
(see Table 3). By allowing system software to control the resetting
of these bits, several operations may be performed (such as
cumulatively writing several bytes or erasing multiple blocks in
sequence). The Status Register may then be polled to determine
if an error occurred during that sequence. This adds flexibility to
the way the device may be used.
Additionally, the V
PP
Status bit (SR.3)
MUST
be reset by system
DEVICE IDENTIFIER COMMAND
Each device contains a device identifier operation, initiated by
writing 90H into the Command User Interface. Following the
command write, a read cycle form address 00000H retrieves the
manufacturer code of 89H. A read cycle form address 000001H
returns, the device code of A2H. To terminate the operation, it
is necessary to write another valid command into the register.
Like the Read Array command, the device identifier command is
functional when V
PP
= V
PPL
or V
PPH
.
software before further byte writes or block erase are
attempted. To clear the Status Register, the Clear Status
Register command (50H) is written to the Command User
Interface. The Clear Status Register command is functional
when V
PP
= V
PPL
or V
PPH
.
ERASE SETUP / ERASE CONFIRM COMMANDS
READ STATUS REGISTER COMMAND
The module contains a Status Register which may be read to
determine when a byte write or block erase operation is complete,
and whether that operation completed successfully. The Status
Register may be read at any time by writing the Read Status
Register command (70H) to the Command User Interface. After
writing this command, all subsequent read operations output data
from the Status Register, until another valid command is written
Erase is executed one block at a time, initiated a two-cycle
command sequence. An Erase Setup command (20H) is first
written to the Command User Interface, followed by the Erase
Confirm command (D0H). These commands require both
appropriate sequencing and an address within the block to be
erased to FFH. Block preconditioning, erase and verify are all
handled internally by the Write State Machine, invisible to the
system. After the two-command erase sequence is written to it,
the device automatically outputs Status Register data when read
(see Figure 3; Block Erase Flowchart). The CPU can detect the
completion of the erase event by analyzing the WSM Status bit of
the Status Register.
Table 2: COMMAND DEFINITION
Command
Read Array/Reset
device Identifier
Read Status Register
Clear Status Register
Erase Setup/Erase Confirm
Erase Suspend/Erase Resume
Byte Write Setup/Write
Alternate Byte Write Setup/Write
Bus
Cycles
Req’d
1
3
2
1
2
2
2
2
First Bus Cycle
Operation
Write
Write
Write
Write
Write
Write
Write
Write
Address
X
X
X
X
BA
X
WA
WA
Data
FFH
90H
70H
50H
20H
B0H
40H
10H
1
Second Bus Cycle
Operation
-
Read
Read
-
Write
Write
Write
Write
Address
-
DA
X
-
BA
X
WA
WA
Data
-
DID
SRD
-
D0H
D0H
WD
WD
1
BA = Address within the block being erased.
DA = Device Address: 00H for manufacturer code, 01H for device code.
DID = Data read from device identifiers.
NOTES:
1.
2.
3.
4.
SRD = Data read from Status Register (see Table 3).
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched on the
rising edge of WE.
Bus operations are defined in Table 2.
Following the device identifier command, two read operations access manufacturer and device codes.
Either 40H or 10H are recognized by WSM as the Byte Write Setup command.
Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
4
30A123-04
REV. D
Dense-Pac Microsystems, Inc.
DPZ4MX16NV3
BYTE WRITE SETUP / WRITE COMMANDS
When erase is completed, the Erase Status bit should be checked.
If erase error is detected, the Status Register should be cleared.
The Command Status Register should be cleared. The command
User Interface remains in Read Status mode until further
commands are issued to it.
This two-step sequence of set-up followed by execution ensures
that memory contents are not accidentally erase. Also, reliable
block erasure can only occur when V
PP
= V
PPH
. In the absence
of this high voltage, memory contents are protected against
erasure. If block erase is attempted while V
PP
= V
PPL
, the V
PP
Status bit will be set to “1”. Erase attempts while V
PPL
< V
PP
<
V
PPH
produce spurious results and should not be attempted.
ERASE SUSPEND / ERASE RESUME COMMANDS
The Erase Suspend command allows block erase interruption in
order to read data from another block of memory. Once the erase
process starts, writing the Erase Suspend command (B0H) to the
Command User Interface requests that the WSM suspend the
erase sequence at a predetermined point in the erase algorithm.
The module continues to output Status Register data when read,
after the Erase Suspend command is written to it. Polling the
WSM status and Erase Suspend status bits will determine when
the erase operation has been suspended (both will be set to “1”).
At this point, a Read Array command can be written to the
command User Interface to read data from blocks other that that
which is suspended. The only other valid commands at this time
are Read Status Register (70H) and Erase Resume (D0H), at which
time the WSM will continue with the erase process. The Erase
Suspend status and WSM status bits of the Status Register will be
automatically cleared. After the Erase Resume command is
written to it, the module automatically outputs Status Register data
when read (see Figure 4; Erase Suspend/Resume Flowchart). V
PP
must remain at V
PPH
while the module is in Erase Suspend.
Byte write is executed by a two-command sequence. The Byte
Write Setup command (40H) is written to the Command User
Interface, followed by a second write specifying the address and
data (latched on the rising edge of WE) to be written. The WSM
then takes over, controlling the byte write and write verify
algorithms internally. After the two-command byte write
sequence is written to it, the module automatically outputs Status
Register data when read (see Figure 2; Automatic Byte Write
Flowchart). The CPU can detect the completion of the byte write
event by analyzing the WSM status bit of the Status Register. Only
the Read Status Register command is valid while byte write is
active.
When byte write is complete, the Byte Write status bit should be
checked. If byte write error is detected the Status Register should
be cleared. The internal WSM verify only detects errors for “1”s
that do not successfully write to “0”s. The Command User
Interface remains in Read Status Register mode until further
commands are issued to it. If byte write is attempted while V
PP
= V
PPL
, the V
PP
Status bit will be set to “1”. Byte write attempts
whole V
PPL
< V
PP
< V
PPH
produce spurious results and should
not be attempted.
AUTOMATED BYTE WRITE
The module integrates programming algorithm on-chip, using the
Command User Interface, Status Register and Write State
Machine (WSM). On-chip integration dramatically simplifies
system software and provides processor interface timings to the
Command User Interface and Status Register. WSM operation,
internal verify and V
PP
high voltage presence are monitored
and reported via the appropriate Status Register bits. Figure
2 shows a system software flowchart for device byte write.
The entire sequence is performed with V
PP
at V
PPH
. Byte write
Table 3: STATUS REGISTER DEFINITIONS
WSMS
7
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
ESS
6
ES
5
BWS
4
VPPS
3
R
2
R
1
R
0
WRITE STATE MACHINE
STATUS
ERASE SUSPEND STATUS
ERASE STATUS
BYTE WRITE STATUS
V
PP
STATUS
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase in Progress/Completed
1 = Error in Block Erase
0 = Successful Block Erase
1 = Error in Byte Write
0 = Successful Byte Write
1 = V
PP
Low Detect;
Operation Abort
0 = V
PP
O.K.
These bits are reserved for
future use and should be
masked out when polling the
Status Register
RESERVED FOR FUTURE
ENHANCEMENTS
NOTES:
The write State Machine Status bit must first be
checked to determine byte write or block erase
completion, before the Byte Write or Erase Status
bit are checked for success.
If the Byte Write AND Erase Status bits are set to
‘’1’’s during a block erase attempt, an improper
command sequence was entered. Attempt the
operation again.
The V
PP
Status bit, unlike an A/D converter, does
not provide continuous indication of V
PP
level.
The WSM interrogates the V
PP
level only after the
byte write or block erase command sequences
have been switched on. The V
PP
Status bit is not
guaranteed to report accurate feedback between
V
PPL
and V
PPH
.
30A123-04
REV. D
5
Analogue and Mixed Signal
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